inter.vho

cpld

-- Copyright (C) 1991-2004 Altera Corporation
-- Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-- support information,  device programming or simulation file,  and any other
-- associated  documentation or information  provided by  Altera  or a partner
-- under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-- to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-- other  use  of such  megafunction  design,  netlist,  support  information,
-- device programming or simulation file,  or any other  related documentation
-- or information  is prohibited  for  any  other purpose,  including, but not
-- limited to  modification,  reverse engineering,  de-compiling, or use  with
-- any other  silicon devices,  unless such use is  explicitly  licensed under
-- a separate agreement with  Altera  or a megafunction partner.  Title to the
-- intellectual property,  including patents,  copyrights,  trademarks,  trade
-- secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-- support  information,  device programming or simulation file,  or any other
-- related documentation or information provided by  Altera  or a megafunction
-- partner, remains with Altera, the megafunction partner, or their respective
-- licensors. No other licenses, including any licenses needed under any third
-- party's intellectual property, are provided herein.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 4.2 Build 156 11/29/2004 SJ Web Edition"

-- DATE "05/09/2006 22:33:56"

-- 
-- Device: Altera EPM3128ATC100-10 Package TQFP100
-- 

-- 
-- This VHDL file should be used for ModelSim (VHDL) only
-- 

LIBRARY IEEE, max;
USE IEEE.std_logic_1164.all;
USE max.max_components.all;

ENTITY 	inter IS
    PORT (
	FPS_INTR : IN std_logic;
	XF : IN std_logic;
	DSP_DS : IN std_logic;
	DSP_PS : IN std_logic;
	IOSTRB : IN std_logic;
	BDX2 : IN std_logic;
	CPLD_GCLRN : IN std_logic;
	CPLD_OE1 : IN std_logic;
	BCLKX2 : IN std_logic;
	BFSX2 : IN std_logic;
	CPLD_TOUT : IN std_logic;
	A15 : IN std_logic;
	A16 : IN std_logic;
	A17 : IN std_logic;
	A18 : IN std_logic;
	DSP_MSTRB : IN std_logic;
	A19 : IN std_logic;
	A20 : IN std_logic;
	DSP_RW : IN std_logic;
	PB_RS : IN std_logic;
	A0 : IN std_logic;
	DSP_IS : IN std_logic;
	FLASH_RY : IN std_logic;
	FPS_WAIT : IN std_logic;
	Key_RESET : IN std_logic;
	Key : IN std_logic;
	CPLD_CLKIN : IN std_logic;
	Key_SDAT : INOUT std_logic;
	DATA_IO : INOUT std_logic_vector(7 DOWNTO 0);
	RS : OUT std_logic;
	INT1 : OUT std_logic;
	INT3 : OUT std_logic;
	NMI : OUT std_logic;
	HOLD : OUT std_logic;
	FLASH_A15 : OUT std_logic;
	FLASH_A16 : OUT std_logic;
	FLASH_A17 : OUT std_logic;
	FLASH_BYTE : OUT std_logic;
	CSROM : OUT std_logic;
	FLASH_WR : OUT std_logic;
	FLASH_RD : OUT std_logic;
	FLASH_RS : OUT std_logic;
	FPS_A0 : OUT std_logic;
	CS_FPS : OUT std_logic;
	FPS_RD : OUT std_logic;
	FPS_WR : OUT std_logic;
	FPS_EXINT : OUT std_logic;
	CSRAM : OUT std_logic;
	BIO : OUT std_logic;
	DSP_READY : OUT std_logic;
	BDR2 : OUT std_logic;
	DSP_Write_INT2 : OUT std_logic;
	Key_CS : OUT std_logic;
	LCD_RS : OUT std_logic;
	LCD_RW : OUT std_logic;
	LCD_E : OUT std_logic;
	LCD_CS1 : OUT std_logic;
	LCD_CS2 : OUT std_logic;
	BCLKR2 : OUT std_logic;
	BFSR2 : OUT std_logic;
	HD0 : OUT std_logic;
	HD1 : OUT std_logic;
	HD2 : OUT std_logic;
	HD3 : OUT std_logic;
	HD4 : OUT std_logic;
	HD5 : OUT std_logic;
	HD6 : OUT std_logic;
	HD7 : OUT std_logic;
	Key_CLKOUT : OUT std_logic
	);
END inter;

ARCHITECTURE structure OF inter IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL ww_FPS_INTR : std_logic;
SIGNAL ww_XF : std_logic;
SIGNAL ww_DSP_DS : std_logic;
SIGNAL ww_DSP_PS : std_logic;
SIGNAL ww_IOSTRB : std_logic;
SIGNAL ww_BDX2 : std_logic;
SIGNAL ww_CPLD_GCLRN : std_logic;
SIGNAL ww_CPLD_OE1 : std_logic;
SIGNAL ww_BCLKX2 : std_logic;
SIGNAL ww_BFSX2 : std_logic;
SIGNAL ww_CPLD_TOUT : std_logic;
SIGNAL ww_A15 : std_logic;
SIGNAL ww_A16 : std_logic;
SIGNAL ww_A17 : std_logic;
SIGNAL ww_A18 : std_logic;
SIGNAL ww_DSP_MSTRB : std_logic;
SIGNAL ww_A19 : std_logic;
SIGNAL ww_A20 : std_logic;
SIGNAL ww_DSP_RW : std_logic;
SIGNAL ww_PB_RS : std_logic;
SIGNAL ww_A0 : std_logic;
SIGNAL ww_DSP_IS : std_logic;
SIGNAL ww_FLASH_RY : std_logic;
SIGNAL ww_FPS_WAIT : std_logic;
SIGNAL ww_Key_RESET : std_logic;
SIGNAL ww_Key : std_logic;
SIGNAL ww_CPLD_CLKIN : std_logic;
SIGNAL ww_RS : std_logic;
SIGNAL ww_INT1 : std_logic;
SIGNAL ww_INT3 : std_logic;
SIGNAL ww_NMI : std_logic;
SIGNAL ww_HOLD : std_logic;
SIGNAL ww_FLASH_A15 : std_logic;
SIGNAL ww_FLASH_A16 : std_logic;
SIGNAL ww_FLASH_A17 : std_logic;
SIGNAL ww_FLASH_BYTE : std_logic;
SIGNAL ww_CSROM : std_logic;
SIGNAL ww_FLASH_WR : std_logic;
SIGNAL ww_FLASH_RD : std_logic;
SIGNAL ww_FLASH_RS : std_logic;
SIGNAL ww_FPS_A0 : std_logic;
SIGNAL ww_CS_FPS : std_logic;
SIGNAL ww_FPS_RD : std_logic;
SIGNAL ww_FPS_WR : std_logic;
SIGNAL ww_FPS_EXINT : std_logic;
SIGNAL ww_CSRAM : std_logic;
SIGNAL ww_BIO : std_logic;
SIGNAL ww_DSP_READY : std_logic;
SIGNAL ww_BDR2 : std_logic;
SIGNAL ww_DSP_Write_INT2 : std_logic;
SIGNAL ww_Key_CS : std_logic;
SIGNAL ww_LCD_RS : std_logic;
SIGNAL ww_LCD_RW : std_logic;
SIGNAL ww_LCD_E : std_logic;
SIGNAL ww_LCD_CS1 : std_logic;
SIGNAL ww_LCD_CS2 : std_logic;
SIGNAL ww_BCLKR2 : std_logic;
SIGNAL ww_BFSR2 : std_logic;
SIGNAL ww_HD0 : std_logic;
SIGNAL ww_HD1 : std_logic;
SIGNAL ww_HD2 : std_logic;
SIGNAL ww_HD3 : std_logic;
SIGNAL ww_HD4 : std_logic;
SIGNAL ww_HD5 : std_logic;
SIGNAL ww_HD6 : std_logic;
SIGNAL ww_HD7 : std_logic;
SIGNAL ww_Key_CLKOUT : std_logic;
SIGNAL A15_a2_I_pterm0_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL A15_a2_I_pterm1_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL A15_a2_I_pterm2_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL A15_a2_I_pterm3_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL A15_a2_I_pterm4_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL A15_a2_I_pterm5_bus : std_logic_vector(51 DOWNTO 0);