📄 inter.fit.rpt
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; ReadKeyValBlock:inst4|Read_Done ; 8 ;
; CLK_DIV:inst6|\Make_CLK:CNT1[1] ; 8 ;
; CLK_DIV:inst6|\Make_CLK:CNT1[2] ; 7 ;
; CLK_DIV:inst6|\Make_CLK:CNT1[3] ; 6 ;
; Key_RESET ; 5 ;
; CLK_DIV:inst6|\Make_CLK:CNT1[4] ; 5 ;
; CLK_DIV:inst6|\Make_CLK:CNT1[5] ; 5 ;
; CLK_DIV:inst6|\Make_CLK:CNT1[6] ; 4 ;
; CLK_DIV:inst6|\Make_CLK:CNT1[7] ; 4 ;
; inst7~42 ; 3 ;
; inst7~41 ; 3 ;
; A18 ; 3 ;
; ReadKeyValBlock:inst4|INPUT_Register[0] ; 3 ;
; ReadKeyValBlock:inst4|INPUT_Register[1] ; 3 ;
; ReadKeyValBlock:inst4|INPUT_Register[2] ; 3 ;
; ReadKeyValBlock:inst4|INPUT_Register[3] ; 3 ;
; ReadKeyValBlock:inst4|INPUT_Register[4] ; 3 ;
; ReadKeyValBlock:inst4|INPUT_Register[5] ; 3 ;
; ReadKeyValBlock:inst4|INPUT_Register[6] ; 3 ;
; CLK_DIV:inst6|\Make_CLK:CNT1[8] ; 3 ;
; DSP_MSTRB ; 2 ;
; inst7~17sexp ; 2 ;
; altdpram0:inst|altdpram:altdpram_component|xql[0]~94 ; 2 ;
; altdpram0:inst|altdpram:altdpram_component|xql[1]~90 ; 2 ;
; altdpram0:inst|altdpram:altdpram_component|xql[2]~86 ; 2 ;
+-------------------------------------------------------------+---------+
+-------------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+--------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+--------------------+
; Output enables ; 1 / 6 ( 16 % ) ;
; PIA buffers ; 120 / 288 ( 41 % ) ;
; PIAs ; 131 / 288 ( 45 % ) ;
+----------------------------+--------------------+
+-----------------------------------------------------------------------------+
; LAB External Interconnect ;
+-----------------------------------------------+-----------------------------+
; LAB External Interconnects (Average = 16.38) ; Number of LABs (Total = 8) ;
+-----------------------------------------------+-----------------------------+
; 0 - 2 ; 0 ;
; 3 - 5 ; 1 ;
; 6 - 8 ; 0 ;
; 9 - 11 ; 0 ;
; 12 - 14 ; 3 ;
; 15 - 17 ; 1 ;
; 18 - 20 ; 1 ;
; 21 - 23 ; 0 ;
; 24 - 26 ; 0 ;
; 27 - 29 ; 2 ;
+-----------------------------------------------+-----------------------------+
+-----------------------------------------------------------------------+
; LAB Macrocells ;
+-----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 11.88) ; Number of LABs (Total = 8) ;
+-----------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 1 ;
; 8 ; 1 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 1 ;
; 14 ; 0 ;
; 15 ; 1 ;
; 16 ; 3 ;
+-----------------------------------------+-----------------------------+
+---------------------------------------------------------+
; Parallel Expander ;
+--------------------------+------------------------------+
; Parallel Expander Length ; Number of Parallel Expanders ;
+--------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 3 ;
+--------------------------+------------------------------+
+-------------------------------------------------------------------------------+
; Shareable Expander ;
+-------------------------------------------------+-----------------------------+
; Number of shareable expanders (Average = 0.63) ; Number of LABs (Total = 5) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 3 ;
; 1 ; 5 ;
+-------------------------------------------------+-----------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC7 ; CPLD_CLKIN, CLK_DIV:inst6|\Make_CLK:CNT1[3], CLK_DIV:inst6|\Make_CLK:CNT1[2], CLK_DIV:inst6|\Make_CLK:CNT1[1], CLK_DIV:inst6|\Make_CLK:CNT1[0], PB_RS ; CLK_DIV:inst6|Key_CLK, CLK_DIV:inst6|\Make_CLK:CNT1[8], CLK_DIV:inst6|\Make_CLK:CNT1[7], CLK_DIV:inst6|\Make_CLK:CNT1[6], CLK_DIV:inst6|\Make_CLK:CNT1[5] ;
; A ; LC6 ; CPLD_CLKIN, CLK_DIV:inst6|\Make_CLK:CNT1[7], CLK_DIV:inst6|\Make_CLK:CNT1[8], CLK_DIV:inst6|\Make_CLK:CNT1[6], CLK_DIV:inst6|\Make_CLK:CNT1[3], CLK_DIV:inst6|\Make_CLK:CNT1[2], CLK_DIV:inst6|\Make_CLK:CNT1[1], CLK_DIV:inst6|\Make_CLK:CNT1[0], CLK_DIV:inst6|\Make_CLK:CNT1[4], CLK_DIV:inst6|\Make_CLK:CNT1[5], PB_RS ; CLK_DIV:inst6|Key_CLK, CLK_DIV:inst6|\Make_CLK:CNT1[8], CLK_DIV:inst6|\Make_CLK:CNT1[7], CLK_DIV:inst6|\Make_CLK:CNT1[6], CLK_DIV:inst6|\Make_CLK:CNT1[5] ;
; A ; LC4 ; CPLD_CLKIN, CLK_DIV:inst6|\Make_CLK:CNT1[5], CLK_DIV:inst6|\Make_CLK:CNT1[4], CLK_DIV:inst6|\Make_CLK:CNT1[3], CLK_DIV:inst6|\Make_CLK:CNT1[2], CLK_DIV:inst6|\Make_CLK:CNT1[1], CLK_DIV:inst6|\Make_CLK:CNT1[0], PB_RS ; CLK_DIV:inst6|Key_CLK, CLK_DIV:inst6|\Make_CLK:CNT1[8], CLK_DIV:inst6|\Make_CLK:CNT1[7], CLK_DIV:inst6|\Make_CLK:CNT1[5] ⌨️ 快捷键说明
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