inter.map.eqn

cpld

--A20 is A20
--operation mode is input

A20 = INPUT();


--DSP_RW is DSP_RW
--operation mode is input

DSP_RW = INPUT();


--PB_RS is PB_RS
--operation mode is input

PB_RS = INPUT();


--A0 is A0
--operation mode is input

A0 = INPUT();


--DSP_IS is DSP_IS
--operation mode is input

DSP_IS = INPUT();


--FLASH_RY is FLASH_RY
--operation mode is input

FLASH_RY = INPUT();


--FPS_WAIT is FPS_WAIT
--operation mode is input

FPS_WAIT = INPUT();


--Key_RESET is Key_RESET
--operation mode is input

Key_RESET = INPUT();


--Key is Key
--operation mode is input

Key = INPUT();


--CPLD_CLKIN is CPLD_CLKIN
--operation mode is input

CPLD_CLKIN = INPUT();


--RS is RS
--operation mode is output

RS = OUTPUT(~VCC~0);


--INT1 is INT1
--operation mode is output

INT1 = OUTPUT(~VCC~1);


--INT3 is INT3
--operation mode is output

INT3 = OUTPUT(~VCC~2);


--NMI is NMI
--operation mode is output

NMI = OUTPUT(~VCC~3);


--HOLD is HOLD
--operation mode is output

HOLD = OUTPUT(~VCC~4);


--FLASH_A15 is FLASH_A15
--operation mode is output

FLASH_A15 = OUTPUT(A1L4);


--FLASH_A16 is FLASH_A16
--operation mode is output

FLASH_A16 = OUTPUT(A1L6);


--FLASH_A17 is FLASH_A17
--operation mode is output

FLASH_A17 = OUTPUT(A1L8);


--FLASH_BYTE is FLASH_BYTE
--operation mode is output

FLASH_BYTE = OUTPUT(~VCC~5);


--CSROM is CSROM
--operation mode is output

CSROM = OUTPUT(C1L2);


--FLASH_WR is FLASH_WR
--operation mode is output

FLASH_WR = OUTPUT(A1L44);


--FLASH_RD is FLASH_RD
--operation mode is output

FLASH_RD = OUTPUT(A1L54);


--FLASH_RS is FLASH_RS
--operation mode is output

FLASH_RS = OUTPUT(A1L88);


--FPS_A0 is FPS_A0
--operation mode is output

FPS_A0 = OUTPUT(A1L2);


--CS_FPS is CS_FPS
--operation mode is output

CS_FPS = OUTPUT(A1L93);


--FPS_RD is FPS_RD
--operation mode is output

FPS_RD = OUTPUT(A1L64);


--FPS_WR is FPS_WR
--operation mode is output

FPS_WR = OUTPUT(A1L74);


--FPS_EXINT is FPS_EXINT
--operation mode is output

FPS_EXINT_open_drain_out = OPNDRN(~VCC~6);
FPS_EXINT = OUTPUT(FPS_EXINT_open_drain_out);


--CSRAM is CSRAM
--operation mode is output

CSRAM = OUTPUT(C1L1);


--BIO is BIO
--operation mode is output

BIO_open_drain_out = OPNDRN(~VCC~7);
BIO = OUTPUT(BIO_open_drain_out);


--DSP_READY is DSP_READY
--operation mode is output

DSP_READY = OUTPUT(C1L3);


--BDR2 is BDR2
--operation mode is output

BDR2_open_drain_out = OPNDRN(~VCC~8);
BDR2 = OUTPUT(BDR2_open_drain_out);


--DSP_Write_INT2 is DSP_Write_INT2
--operation mode is output

DSP_Write_INT2 = OUTPUT(E1_DSP_Write_INT);


--Key_CS is Key_CS
--operation mode is output

Key_CS = OUTPUT(D1L8);


--LCD_RS is LCD_RS
--operation mode is output

LCD_RS_tri_out = TRI(A1L01, GND);
LCD_RS = OUTPUT(LCD_RS_tri_out);


--LCD_RW is LCD_RW
--operation mode is output

LCD_RW_open_drain_out = OPNDRN(~VCC~9);
LCD_RW = OUTPUT(LCD_RW_open_drain_out);


--LCD_E is LCD_E
--operation mode is output

LCD_E = OUTPUT(~VCC~10);


--LCD_CS1 is LCD_CS1
--operation mode is output

LCD_CS1_open_drain_out = OPNDRN(~VCC~11);
LCD_CS1 = OUTPUT(LCD_CS1_open_drain_out);


--LCD_CS2 is LCD_CS2
--operation mode is output

LCD_CS2 = OUTPUT(~GND~0);


--BCLKR2 is BCLKR2
--operation mode is output

BCLKR2_open_drain_out = OPNDRN(~VCC~12);
BCLKR2 = OUTPUT(BCLKR2_open_drain_out);


--BFSR2 is BFSR2
--operation mode is output

BFSR2_open_drain_out = OPNDRN(~VCC~13);
BFSR2 = OUTPUT(BFSR2_open_drain_out);


--HD0 is HD0
--operation mode is output

HD0_open_drain_out = OPNDRN(~VCC~14);
HD0 = OUTPUT(HD0_open_drain_out);


--HD1 is HD1
--operation mode is output

HD1_open_drain_out = OPNDRN(~VCC~15);
HD1 = OUTPUT(HD1_open_drain_out);


--HD2 is HD2
--operation mode is output

HD2_open_drain_out = OPNDRN(~VCC~16);
HD2 = OUTPUT(HD2_open_drain_out);


--HD3 is HD3
--operation mode is output

HD3_open_drain_out = OPNDRN(~VCC~17);
HD3 = OUTPUT(HD3_open_drain_out);


--HD4 is HD4
--operation mode is output

HD4_open_drain_out = OPNDRN(~VCC~18);
HD4 = OUTPUT(HD4_open_drain_out);


--HD5 is HD5
--operation mode is output

HD5_open_drain_out = OPNDRN(~VCC~19);
HD5 = OUTPUT(HD5_open_drain_out);


--HD6 is HD6
--operation mode is output

HD6_open_drain_out = OPNDRN(~VCC~20);
HD6 = OUTPUT(HD6_open_drain_out);


--HD7 is HD7
--operation mode is output

HD7 = OUTPUT(G1_Key_CLK);


--Key_CLKOUT is Key_CLKOUT
--operation mode is output

Key_CLKOUT = OUTPUT(D1L3);


--dat is dat
--operation mode is bidir

dat = Key_SDAT;

--Key_SDAT is Key_SDAT
--operation mode is bidir

Key_SDAT_tri_out = TRI(D1L9Q, D1L11Q);
Key_SDAT = BIDIR(Key_SDAT_tri_out);


--DATA_IO[7] is DATA_IO[7]
--operation mode is bidir

DATA_IO[7]_tri_out = TRI(H1L8, VCC);
DATA_IO[7] = BIDIR(DATA_IO[7]_tri_out);


--DATA_IO[6] is DATA_IO[6]
--operation mode is bidir

DATA_IO[6]_tri_out = TRI(H1L7, VCC);
DATA_IO[6] = BIDIR(DATA_IO[6]_tri_out);


--DATA_IO[5] is DATA_IO[5]
--operation mode is bidir

DATA_IO[5]_tri_out = TRI(H1L6, VCC);
DATA_IO[5] = BIDIR(DATA_IO[5]_tri_out);


--DATA_IO[4] is DATA_IO[4]
--operation mode is bidir

DATA_IO[4]_tri_out = TRI(H1L5, VCC);
DATA_IO[4] = BIDIR(DATA_IO[4]_tri_out);


--DATA_IO[3] is DATA_IO[3]
--operation mode is bidir

DATA_IO[3]_tri_out = TRI(H1L4, VCC);
DATA_IO[3] = BIDIR(DATA_IO[3]_tri_out);


--DATA_IO[2] is DATA_IO[2]
--operation mode is bidir

DATA_IO[2]_tri_out = TRI(H1L3, VCC);
DATA_IO[2] = BIDIR(DATA_IO[2]_tri_out);


--DATA_IO[1] is DATA_IO[1]
--operation mode is bidir

DATA_IO[1]_tri_out = TRI(H1L2, VCC);
DATA_IO[1] = BIDIR(DATA_IO[1]_tri_out);


--DATA_IO[0] is DATA_IO[0]
--operation mode is bidir

DATA_IO[0]_tri_out = TRI(H1L1, VCC);
DATA_IO[0] = BIDIR(DATA_IO[0]_tri_out);