inter.fit.eqn

cpld

E1_INPUT_Register[7] = TFFE(E1_INPUT_Register[7]_reg_input, !G1_Key_CLK, , , );


--E1_Read_Done is ReadKeyValBlock:inst4|Read_Done at LC52
E1_Read_Done_p1_out = P2_dffs[3] & !P2_dffs[5] & !P2_dffs[7] & !P2_dffs[4] & !P2_dffs[6] & !P2_dffs[1] & !P2_dffs[2] & !P2_dffs[0];
E1_Read_Done_or_out = E1_Read_Done_p1_out;
E1_Read_Done_reg_input = E1_Read_Done_or_out;
E1_Read_Done = DFFE(E1_Read_Done_reg_input, !G1_Key_CLK, , , );


--E1_INPUT_Register[6] is ReadKeyValBlock:inst4|INPUT_Register[6] at LC79
E1_INPUT_Register[6]_p0_out = !E1_INPUT_Register[5] & !P2_dffs[3] & D1_Read_En & !P2_dffs[5] & !P2_dffs[7] & !P2_dffs[4] & !P2_dffs[6] & E1_INPUT_Register[6];
E1_INPUT_Register[6]_p1_out = E1_INPUT_Register[5] & !P2_dffs[3] & D1_Read_En & !P2_dffs[5] & !P2_dffs[7] & !P2_dffs[4] & !P2_dffs[6] & !E1_INPUT_Register[6];
E1_INPUT_Register[6]_p2_out = E1_INPUT_Register[5] & D1_Read_En & !P2_dffs[5] & !P2_dffs[7] & !P2_dffs[4] & !P2_dffs[6] & !E1_INPUT_Register[6] & !P2_dffs[1] & !P2_dffs[2] & !P2_dffs[0];
E1_INPUT_Register[6]_p4_out = !E1_INPUT_Register[5] & D1_Read_En & !P2_dffs[5] & !P2_dffs[7] & !P2_dffs[4] & !P2_dffs[6] & E1_INPUT_Register[6] & !P2_dffs[1] & !P2_dffs[2] & !P2_dffs[0];
E1_INPUT_Register[6]_or_out = E1_INPUT_Register[6]_p0_out # E1_INPUT_Register[6]_p1_out # E1_INPUT_Register[6]_p2_out # E1_INPUT_Register[6]_p4_out;
E1_INPUT_Register[6]_reg_input = E1_INPUT_Register[6]_or_out;
E1_INPUT_Register[6] = TFFE(E1_INPUT_Register[6]_reg_input, !G1_Key_CLK, , , );


--E1_INPUT_Register[5] is ReadKeyValBlock:inst4|INPUT_Register[5] at LC76
E1_INPUT_Register[5]_p0_out = !E1_INPUT_Register[4] & !P2_dffs[3] & D1_Read_En & !P2_dffs[5] & !P2_dffs[7] & !P2_dffs[4] & !P2_dffs[6] & E1_INPUT_Register[5];
E1_INPUT_Register[5]_p1_out = E1_INPUT_Register[4] & !P2_dffs[3] & D1_Read_En & !P2_dffs[5] & !P2_dffs[7] & !P2_dffs[4] & !P2_dffs[6] & !E1_INPUT_Register[5];
E1_INPUT_Register[5]_p2_out = E1_INPUT_Register[4] & D1_Read_En & !P2_dffs[5] & !P2_dffs[7] & !P2_dffs[4] & !P2_dffs[6] & !E1_INPUT_Register[5] & !P2_dffs[1] & !P2_dffs[2] & !P2_dffs[0];
E1_INPUT_Register[5]_p4_out = !E1_INPUT_Register[4] & D1_Read_En & !P2_dffs[5] & !P2_dffs[7] & !P2_dffs[4] & !P2_dffs[6] & E1_INPUT_Register[5] & !P2_dffs[1] & !P2_dffs[2] & !P2_dffs[0];
E1_INPUT_Register[5]_or_out = E1_INPUT_Register[5]_p0_out # E1_INPUT_Register[5]_p1_out # E1_INPUT_Register[5]_p2_out # E1_INPUT_Register[5]_p4_out;
E1_INPUT_Register[5]_reg_input = E1_INPUT_Register[5]_or_out;
E1_INPUT_Register[5] = TFFE(E1_INPUT_Register[5]_reg_input, !G1_Key_CLK, , , );


--E1_INPUT_Register[4] is ReadKeyValBlock:inst4|INPUT_Register[4] at LC68
E1_INPUT_Register[4]_p0_out = !E1_INPUT_Register[3] & !P2_dffs[3] & D1_Read_En & !P2_dffs[5] & !P2_dffs[7] & !P2_dffs[4] & !P2_dffs[6] & E1_INPUT_Register[4];
E1_INPUT_Register[4]_p1_out = E1_INPUT_Register[3] & !P2_dffs[3] & D1_Read_En & !P2_dffs[5] & !P2_dffs[7] & !P2_dffs[4] & !P2_dffs[6] & !E1_INPUT_Register[4];
E1_INPUT_Register[4]_p2_out = E1_INPUT_Register[3] & D1_Read_En & !P2_dffs[5] & !P2_dffs[7] & !P2_dffs[4] & !P2_dffs[6] & !E1_INPUT_Register[4] & !P2_dffs[1] & !P2_dffs[2] & !P2_dffs[0];
E1_INPUT_Register[4]_p4_out = !E1_INPUT_Register[3] & D1_Read_En & !P2_dffs[5] & !P2_dffs[7] & !P2_dffs[4] & !P2_dffs[6] & E1_INPUT_Register[4] & !P2_dffs[1] & !P2_dffs[2] & !P2_dffs[0];
E1_INPUT_Register[4]_or_out = E1_INPUT_Register[4]_p0_out # E1_INPUT_Register[4]_p1_out # E1_INPUT_Register[4]_p2_out # E1_INPUT_Register[4]_p4_out;
E1_INPUT_Register[4]_reg_input = E1_INPUT_Register[4]_or_out;
E1_INPUT_Register[4] = TFFE(E1_INPUT_Register[4]_reg_input, !G1_Key_CLK, , , );


--E1_INPUT_Register[3] is ReadKeyValBlock:inst4|INPUT_Register[3] at LC127
E1_INPUT_Register[3]_p0_out = !E1_INPUT_Register[2] & !P2_dffs[3] & D1_Read_En & !P2_dffs[5] & !P2_dffs[7] & !P2_dffs[4] & !P2_dffs[6] & E1_INPUT_Register[3];
E1_INPUT_Register[3]_p1_out = E1_INPUT_Register[2] & !P2_dffs[3] & D1_Read_En & !P2_dffs[5] & !P2_dffs[7] & !P2_dffs[4] & !P2_dffs[6] & !E1_INPUT_Register[3];
E1_INPUT_Register[3]_p2_out = E1_INPUT_Register[2] & D1_Read_En & !P2_dffs[5] & !P2_dffs[7] & !P2_dffs[4] & !P2_dffs[6] & !E1_INPUT_Register[3] & !P2_dffs[1] & !P2_dffs[2] & !P2_dffs[0];
E1_INPUT_Register[3]_p4_out = !E1_INPUT_Register[2] & D1_Read_En & !P2_dffs[5] & !P2_dffs[7] & !P2_dffs[4] & !P2_dffs[6] & E1_INPUT_Register[3] & !P2_dffs[1] & !P2_dffs[2] & !P2_dffs[0];
E1_INPUT_Register[3]_or_out = E1_INPUT_Register[3]_p0_out # E1_INPUT_Register[3]_p1_out # E1_INPUT_Register[3]_p2_out # E1_INPUT_Register[3]_p4_out;
E1_INPUT_Register[3]_reg_input = E1_INPUT_Register[3]_or_out;
E1_INPUT_Register[3] = TFFE(E1_INPUT_Register[3]_reg_input, !G1_Key_CLK, , , );


--E1_INPUT_Register[2] is ReadKeyValBlock:inst4|INPUT_Register[2] at LC116
E1_INPUT_Register[2]_p0_out = !E1_INPUT_Register[1] & !P2_dffs[3] & D1_Read_En & !P2_dffs[5] & !P2_dffs[7] & !P2_dffs[4] & !P2_dffs[6] & E1_INPUT_Register[2];
E1_INPUT_Register[2]_p1_out = E1_INPUT_Register[1] & !P2_dffs[3] & D1_Read_En & !P2_dffs[5] & !P2_dffs[7] & !P2_dffs[4] & !P2_dffs[6] & !E1_INPUT_Register[2];
E1_INPUT_Register[2]_p2_out = E1_INPUT_Register[1] & D1_Read_En & !P2_dffs[5] & !P2_dffs[7] & !P2_dffs[4] & !P2_dffs[6] & !E1_INPUT_Register[2] & !P2_dffs[1] & !P2_dffs[2] & !P2_dffs[0];
E1_INPUT_Register[2]_p4_out = !E1_INPUT_Register[1] & D1_Read_En & !P2_dffs[5] & !P2_dffs[7] & !P2_dffs[4] & !P2_dffs[6] & E1_INPUT_Register[2] & !P2_dffs[1] & !P2_dffs[2] & !P2_dffs[0];
E1_INPUT_Register[2]_or_out = E1_INPUT_Register[2]_p0_out # E1_INPUT_Register[2]_p1_out # E1_INPUT_Register[2]_p2_out # E1_INPUT_Register[2]_p4_out;
E1_INPUT_Register[2]_reg_input = E1_INPUT_Register[2]_or_out;
E1_INPUT_Register[2] = TFFE(E1_INPUT_Register[2]_reg_input, !G1_Key_CLK, , , );


--E1_INPUT_Register[1] is ReadKeyValBlock:inst4|INPUT_Register[1] at LC119
E1_INPUT_Register[1]_p0_out = !E1_INPUT_Register[0] & !P2_dffs[3] & D1_Read_En & !P2_dffs[5] & !P2_dffs[7] & !P2_dffs[4] & !P2_dffs[6] & E1_INPUT_Register[1];
E1_INPUT_Register[1]_p1_out = E1_INPUT_Register[0] & !P2_dffs[3] & D1_Read_En & !P2_dffs[5] & !P2_dffs[7] & !P2_dffs[4] & !P2_dffs[6] & !E1_INPUT_Register[1];
E1_INPUT_Register[1]_p2_out = E1_INPUT_Register[0] & D1_Read_En & !P2_dffs[5] & !P2_dffs[7] & !P2_dffs[4] & !P2_dffs[6] & !E1_INPUT_Register[1] & !P2_dffs[1] & !P2_dffs[2] & !P2_dffs[0];
E1_INPUT_Register[1]_p4_out = !E1_INPUT_Register[0] & D1_Read_En & !P2_dffs[5] & !P2_dffs[7] & !P2_dffs[4] & !P2_dffs[6] & E1_INPUT_Register[1] & !P2_dffs[1] & !P2_dffs[2] & !P2_dffs[0];
E1_INPUT_Register[1]_or_out = E1_INPUT_Register[1]_p0_out # E1_INPUT_Register[1]_p1_out # E1_INPUT_Register[1]_p2_out # E1_INPUT_Register[1]_p4_out;
E1_INPUT_Register[1]_reg_input = E1_INPUT_Register[1]_or_out;
E1_INPUT_Register[1] = TFFE(E1_INPUT_Register[1]_reg_input, !G1_Key_CLK, , , );


--E1_INPUT_Register[0] is ReadKeyValBlock:inst4|INPUT_Register[0] at LC63
E1_INPUT_Register[0]_p0_out = !dat & !P2_dffs[3] & D1_Read_En & !P2_dffs[5] & !P2_dffs[7] & !P2_dffs[4] & !P2_dffs[6] & E1_INPUT_Register[0];
E1_INPUT_Register[0]_p1_out = dat & !P2_dffs[3] & D1_Read_En & !P2_dffs[5] & !P2_dffs[7] & !P2_dffs[4] & !P2_dffs[6] & !E1_INPUT_Register[0];
E1_INPUT_Register[0]_p2_out = dat & D1_Read_En & !P2_dffs[5] & !P2_dffs[7] & !P2_dffs[4] & !P2_dffs[6] & !E1_INPUT_Register[0] & !P2_dffs[1] & !P2_dffs[2] & !P2_dffs[0];
E1_INPUT_Register[0]_p4_out = !dat & D1_Read_En & !P2_dffs[5] & !P2_dffs[7] & !P2_dffs[4] & !P2_dffs[6] & E1_INPUT_Register[0] & !P2_dffs[1] & !P2_dffs[2] & !P2_dffs[0];
E1_INPUT_Register[0]_or_out = E1_INPUT_Register[0]_p0_out # E1_INPUT_Register[0]_p1_out # E1_INPUT_Register[0]_p2_out # E1_INPUT_Register[0]_p4_out;
E1_INPUT_Register[0]_reg_input = E1_INPUT_Register[0]_or_out;
E1_INPUT_Register[0] = TFFE(E1_INPUT_Register[0]_reg_input, !G1_Key_CLK, , , );


--H1L8 is altdpram0:inst|altdpram:altdpram_component|xql[7]~66 at LC11
H1L8_p1_out = !A0 & E1_Key_Data[7] & !A20 & A15 & DSP_RW & A19;
H1L8_p2_out = H1L8 & A1L27;
H1L8_p3_out = H1L8 & !A0 & E1_Key_Data[7];
H1L8_or_out = H1L8_p1_out # H1L8_p2_out # H1L8_p3_out;
H1L8 = H1L8_or_out;


--H1L7 is altdpram0:inst|altdpram:altdpram_component|xql[6]~70 at LC13
H1L7_p1_out = !A20 & A15 & DSP_RW & A19 & !A0 & E1_Key_Data[6];
H1L7_p2_out = H1L7 & A1L27;
H1L7_p3_out = H1L7 & !A0 & E1_Key_Data[6];
H1L7_or_out = H1L7_p1_out # H1L7_p2_out # H1L7_p3_out;
H1L7 = H1L7_or_out;


--H1L6 is altdpram0:inst|altdpram:altdpram_component|xql[5]~74 at LC102
H1L6_p1_out = !A20 & A15 & DSP_RW & A19 & !A0 & E1_Key_Data[5];
H1L6_p2_out = H1L6 & A1L37;
H1L6_p3_out = H1L6 & !A0 & E1_Key_Data[5];
H1L6_or_out = H1L6_p1_out # H1L6_p2_out # H1L6_p3_out;
H1L6 = H1L6_or_out;


--H1L5 is altdpram0:inst|altdpram:altdpram_component|xql[4]~78 at LC99
H1L5_p1_out = !A20 & A15 & DSP_RW & A19 & !A0 & E1_Key_Data[4];
H1L5_p2_out = H1L5 & A1L37;
H1L5_p3_out = H1L5 & !A0 & E1_Key_Data[4];
H1L5_or_out = H1L5_p1_out # H1L5_p2_out # H1L5_p3_out;
H1L5 = H1L5_or_out;


--H1L4 is altdpram0:inst|altdpram:altdpram_component|xql[3]~82 at LC97
H1L4_p1_out = !A20 & A15 & DSP_RW & A19 & !A0 & E1_Key_Data[3];
H1L4_p2_out = H1L4 & A1L37;
H1L4_p3_out = H1L4 & !A0 & E1_Key_Data[3];
H1L4_or_out = H1L4_p1_out # H1L4_p2_out # H1L4_p3_out;
H1L4 = H1L4_or_out;


--H1L3 is altdpram0:inst|altdpram:altdpram_component|xql[2]~86 at LC94
H1L3_p1_out = !A20 & A15 & DSP_RW & A19 & !A0 & E1_Key_Data[2];
H1L3_p2_out = H1L3 & A1L47;
H1L3_p3_out = H1L3 & !A0 & E1_Key_Data[2];
H1L3_or_out = H1L3_p1_out # H1L3_p2_out # H1L3_p3_out;
H1L3 = H1L3_or_out;


--H1L2 is altdpram0:inst|altdpram:altdpram_component|xql[1]~90 at LC93
H1L2_p1_out = !A20 & A15 & DSP_RW & A19 & !A0 & E1_Key_Data[1];
H1L2_p2_out = H1L2 & A1L47;
H1L2_p3_out = H1L2 & !A0 & E1_Key_Data[1];
H1L2_or_out = H1L2_p1_out # H1L2_p2_out # H1L2_p3_out;
H1L2 = H1L2_or_out;


--H1L1 is altdpram0:inst|altdpram:altdpram_component|xql[0]~94 at LC91
H1L1_p1_out = !A20 & A15 & DSP_RW & A19 & !A0 & E1_Key_Data[0];
H1L1_p2_out = H1L1 & A1L47;
H1L1_p3_out = H1L1 & !A0 & E1_Key_Data[0];
H1L1_or_out = H1L1_p1_out # H1L1_p2_out # H1L1_p3_out;
H1L1 = H1L1_or_out;


--D1L5 is Send_CMD_7279A:inst3|Key_CLKOUT~471 at LC114
D1L5_p1_out = G1_Key_CLK & !P1_dffs[1] & P1_dffs[0] & !P1_dffs[4];
D1L5_p2_out = G1_Key_CLK & P1_dffs[1] & !P1_dffs[4] & !P1_dffs[3];
D1L5_p3_out = G1_Key_CLK & P1_dffs[4] & !P1_dffs[3] & !P1_dffs[2];
D1L5_p4_out = G1_Key_CLK & !P1_dffs[1] & !P1_dffs[0] & !P1_dffs[3] & P1_dffs[2];
D1L5 = D1L5_p1_out # D1L5_p2_out # D1L5_p3_out # D1L5_p4_out;


--D1L1 is Send_CMD_7279A:inst3|add~146 at LC25
D1L1_p1_out = !Key_RESET & !D1_Key_CS_Delay[1];
D1L1 = D1L1_p1_out;


--P1L1 is Send_CMD_7279A:inst3|lpm_counter:Transmit_Cnt_rtl_0|_~203 at LC19
P1L1_p1_out = !P1_dffs[4] & P1_dffs[0];
P1L1 = P1L1_p1_out;


--~VCC~0 is ~VCC~0 at LC89
~VCC~0_or_out = GND;
~VCC~0 = !(~VCC~0_or_out);


--~VCC~1 is ~VCC~1 at LC49
~VCC~1_or_out = GND;
~VCC~1 = !(~VCC~1_or_out);


--~VCC~2 is ~VCC~2 at LC67
~VCC~2_or_out = GND;
~VCC~2 = !(~VCC~2_or_out);


--~VCC~3 is ~VCC~3 at LC51
~VCC~3_or_out = GND;
~VCC~3 = !(~VCC~3_or_out);


--~VCC~4 is ~VCC~4 at LC46
~VCC~4_or_out = GND;
~VCC~4 = !(~VCC~4_or_out);


--~VCC~5 is ~VCC~5 at LC81
~VCC~5_or_out = GND;
~VCC~5 = !(~VCC~5_or_out);


--~VCC~6 is ~VCC~6 at LC33
~VCC~6_or_out = GND;
~VCC~6 = !(~VCC~6_or_out);


--~VCC~7 is ~VCC~7 at LC45
~VCC~7_or_out = GND;
~VCC~7 = !(~VCC~7_or_out);


--~VCC~8 is ~VCC~8 at LC61
~VCC~8_or_out = GND;
~VCC~8 = !(~VCC~8_or_out);


--~VCC~9 is ~VCC~9 at LC128
~VCC~9_or_out = GND;
~VCC~9 = !(~VCC~9_or_out);


--~VCC~10 is ~VCC~10 at LC125
~VCC~10_or_out = GND;
~VCC~10 = !(~VCC~10_or_out);


--~VCC~11 is ~VCC~11 at LC121
~VCC~11_or_out = GND;
~VCC~11 = !(~VCC~11_or_out);


--~GND~0 is ~GND~0 at LC123
~GND~0_or_out = GND;
~GND~0 = ~GND~0_or_out;


--~VCC~12 is ~VCC~12 at LC64
~VCC~12_or_out = GND;
~VCC~12 = !(~VCC~12_or_out);


--~VCC~13 is ~VCC~13 at LC62
~VCC~13_or_out = GND;
~VCC~13 = !(~VCC~13_or_out);


--~VCC~14 is ~VCC~14 at LC56
~VCC~14_or_out = GND;
~VCC~14 = !(~VCC~14_or_out);


--~VCC~15 is ~VCC~15 at LC69
~VCC~15_or_out = GND;
~VCC~15 = !(~VCC~15_or_out);


--~VCC~16 is ~VCC~16 at LC86
~VCC~16_or_out = GND;
~VCC~16 = !(~VCC~16_or_out);


--~VCC~17 is ~VCC~17 at LC88
~VCC~17_or_out = GND;
~VCC~17 = !(~VCC~17_or_out);


--~VCC~18 is ~VCC~18 at LC9
~VCC~18_or_out = GND;
~VCC~18 = !(~VCC~18_or_out);


--~VCC~19 is ~VCC~19 at LC8
~VCC~19_or_out = GND;
~VCC~19 = !(~VCC~19_or_out);


--~VCC~20 is ~VCC~20 at LC5
~VCC~20_or_out = GND;
~VCC~20 = !(~VCC~20_or_out);


--A1L27 is inst7~17sexp at SEXP1
A1L27 = EXP(!A20 & A15 & DSP_RW & A19);


--FPS_INTR is FPS_INTR at PIN_24
--operation mode is input

FPS_INTR = INPUT();


--XF is XF at PIN_14
--operation mode is input

XF = INPUT();


--DSP_DS is DSP_DS at PIN_8
--operation mode is input

DSP_DS = INPUT();


--DSP_PS is DSP_PS at PIN_7
--operation mode is input

DSP_PS = INPUT();


--IOSTRB is IOSTRB at PIN_13
--operation mode is input

IOSTRB = INPUT();


--BDX2 is BDX2 at PIN_35
--operation mode is input

BDX2 = INPUT();


--CPLD_GCLRN is CPLD_GCLRN at PIN_89
--operation mode is input

CPLD_GCLRN = INPUT();


--CPLD_OE1 is CPLD_OE1 at PIN_88
--operation mode is input

CPLD_OE1 = INPUT();


--BCLKX2 is BCLKX2 at PIN_30
--operation mode is input

BCLKX2 = INPUT();


--BFSX2 is BFSX2 at PIN_31
--operation mode is input

BFSX2 = INPUT();


--CPLD_TOUT is CPLD_TOUT at PIN_87
--operation mode is input

CPLD_TOUT = INPUT();


--A15 is A15 at PIN_5
--operation mode is input

A15 = INPUT();


--A16 is A16 at PIN_68
--operation mode is input

A16 = INPUT();


--A17 is A17 at PIN_69
--operation mode is input

A17 = INPUT();


--A18 is A18 at PIN_70
--operation mode is input

A18 = INPUT();


--DSP_MSTRB is DSP_MSTRB at PIN_12
--operation mode is input

DSP_MSTRB = INPUT();


--A19 is A19 at PIN_92
--operation mode is input

A19 = INPUT();


--A20 is A20 at PIN_93
--operation mode is input

A20 = INPUT();


--DSP_RW is DSP_RW at PIN_10
--operation mode is input

DSP_RW = INPUT();