clk_div.vhd

cpld

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-- Generated by Quartus II Version 4.2 (Build Build 156 11/29/2004)
-- Created on Sun May 29 22:35:14 2005

LIBRARY ieee;
USE ieee.std_logic_1164.all;


--  Entity Declaration

ENTITY CLK_DIV IS
	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	PORT
	(
		CPLD_CLKIN : IN STD_LOGIC;
		PB_RS : IN STD_LOGIC;
		Key_CLK : OUT STD_LOGIC

	);
	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	
END CLK_DIV;


--  Architecture Body

ARCHITECTURE CLK_DIV_architecture OF CLK_DIV IS
SIGNAL  CLK:STD_LOGIC;
CONSTANT DIV_NUM:INTEGER:=160;
--400=>脉冲宽度20uS
--300=>脉冲宽度15uS
--200=>脉冲宽度10uS
--100=>脉冲宽度5uS
--60=>脉冲宽度3uS
--40=>脉冲宽度2uS


BEGIN
   
Make_CLK:
PROCESS (PB_RS,CPLD_CLKIN)
	
	VARIABLE CNT1 :INTEGER RANGE 0 TO 310;
	
    BEGIN
	-- Toggle txclk every 160 counts, which divides the clock by 320
	IF PB_RS='0' THEN
	
	    CLK <= '0' ;
	  
	    CNT1 := 0 ;
	  
	
	ELSIF rising_edge(CPLD_CLKIN) THEN
	
	      IF (CNT1 = DIV_NUM) THEN 
	       
	         CNT1:=0;
	         CLK <= NOT CLK; 
	 
	     END IF;
	
	     CNT1 := CNT1 + 1; -- Use the exemplar_1164 "+" on std_logic_vector
 
         
	END IF;

 END PROCESS  Make_CLK;
  
   Key_CLK<=CLK;

END CLK_DIV_architecture;