automake.log

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Writing Analyst data base generic.srm
Reading Generic I/O pad type table from file <D:\ISPTOOLS5_1\SYNPBASE\lib/Generic/x_io_tbl.txt> 
Reading Generic I/O pad type table from file <D:\ISPTOOLS5_1\SYNPBASE\lib/Generic/x_io_tbl.txt> 
Reading Generic I/O pad type table from file <D:\ISPTOOLS5_1\SYNPBASE\lib/Generic/x_io_tbl.txt> 
Reading Generic I/O pad type table from file <D:\ISPTOOLS5_1\SYNPBASE\lib/Generic/x_io_tbl.txt> 
Process took 0h:00m:05s realtime, 0h:00m:04s cputime
# Fri Jul 07 14:16:33 2006

###########################################################]
Automatic dissolve at startup in view:work.UART_FIFO(netlist) of u0(dpram16x8)
Automatic dissolve at startup in view:work.txmit_u3(netlist) of u0(UART_FIFO)
Automatic dissolve at startup in view:work.UART_FIFO_1(netlist) of u0(dpram16x8_1)
Automatic dissolve at startup in view:work.txmit_u3_1(netlist) of u0(UART_FIFO_1)
Automatic dissolve at startup in view:work.UART_FIFO_2(netlist) of u0(dpram16x8_2)
Automatic dissolve at startup in view:work.txmit_u3_2(netlist) of u0(UART_FIFO_2)
Automatic dissolve at startup in view:work.UART_FIFO_3(netlist) of u0(dpram16x8_3)
Automatic dissolve at startup in view:work.txmit_u3_3(netlist) of u0(UART_FIFO_3)
Automatic dissolve at startup in view:work.UART_FIFO_4(netlist) of u0(dpram16x8_4)
Automatic dissolve at startup in view:work.rcvr_u7(netlist) of u1(UART_FIFO_4)
Automatic dissolve at startup in view:work.UART_FIFO_5(netlist) of u0(dpram16x8_5)
Automatic dissolve at startup in view:work.rcvr_u7_1(netlist) of u1(UART_FIFO_5)
Automatic dissolve at startup in view:work.UART_FIFO_6(netlist) of u0(dpram16x8_6)
Automatic dissolve at startup in view:work.rcvr_u7_2(netlist) of u1(UART_FIFO_6)
Automatic dissolve at startup in view:work.UART_FIFO_7(netlist) of u0(dpram16x8_7)
Automatic dissolve at startup in view:work.rcvr_u7_3(netlist) of u1(UART_FIFO_7)
Automatic dissolve at startup in view:work.Uart4(verilog) of u13(data_path)
Automatic dissolve at startup in view:work.Uart4(verilog) of u12(inter)
Automatic dissolve at startup in view:work.Uart4(verilog) of u2(baud)
Automatic dissolve at startup in view:work.Uart4(verilog) of u1(decode)

Note:  Found multiple reset signals.  This prevents
Automatic selection of a Global Reset Signal (GSR).
A possible cause is that the reset signal has multiple
top level net names by stitching through a lower level of hierarchy.
and then coming back up through another port.
An attribute of syn_hier="remove" on the module/architecture
will allow Synplify to merge the reset signals.

@N: FO100 :"e:\yiluo\dd\uart4_top.v":7:6:7:8|Reset 0: "rst" in work.Uart4(verilog) 
@N: FO100 :|Reset 1: "N_13_i" in work.rcvr_u7_1(netlist) 
@N: FO100 :|Reset 2: "N_13_i" in work.rcvr_u7_3(netlist) 
@N: FO100 :|Reset 3: "N_13_i" in work.rcvr_u7_2(netlist) 
@N: FO100 :|Reset 4: "N_13_i" in work.rcvr_u7(netlist) 

@W: BN132 :"e:\yiluo\dd\rcvr.v":26:10:26:11|Removing instance u8.u1.FF,  because it is equivalent to instance u13.un1_FF1_m0_0_bm[0]
@W: BN132 :"e:\yiluo\dd\rcvr.v":26:10:26:11|Removing instance u8.u1.EF,  because it is equivalent to instance u13.un1_EF1_m0_0_bm[3]
@W: BN132 :"e:\yiluo\dd\uart4_top.v":51:6:51:7|Removing instance u5.tmpc,  because it is equivalent to instance u6.tmpc
@W: BN132 :"e:\yiluo\dd\txmit.v":48:10:48:11|Removing instance u5.u0.FF,  because it is equivalent to instance u13.un1_FF0_m1_0_am[4]
@W: BN132 :"e:\yiluo\dd\txmit.v":48:10:48:11|Removing instance u6.u0.EF,  because it is equivalent to instance u13.un1_EF1_m1_0_am[3]
@W: BN132 :"e:\yiluo\dd\txmit.v":48:10:48:11|Removing instance u6.u0.FF,  because it is equivalent to instance u13.un1_FF1_m1_0_am[0]
@W: BN132 :"e:\yiluo\dd\txmit.v":48:10:48:11|Removing instance u3.u0.FF,  because it is equivalent to instance u13.un1_FF0_m1_0_bm[4]
@W: BN132 :"e:\yiluo\dd\txmit.v":48:10:48:11|Removing instance u4.u0.FF,  because it is equivalent to instance u13.un1_FF1_m1_0_bm[0]
@W: BN132 :"e:\yiluo\dd\txmit.v":48:10:48:11|Removing instance u4.u0.EF,  because it is equivalent to instance u13.un1_EF1_m1_0_bm[3]
@W: BN132 :"e:\yiluo\dd\rcvr.v":26:10:26:11|Removing instance u9.u1.FF,  because it is equivalent to instance u13.un1_FF0_m0_0_am[4]
@W: BN132 :"e:\yiluo\dd\rcvr.v":26:10:26:11|Removing instance u10.u1.FF,  because it is equivalent to instance u13.un1_FF1_m0_0_am[0]
@W: BN132 :"e:\yiluo\dd\rcvr.v":26:10:26:11|Removing instance u7.u1.FF,  because it is equivalent to instance u13.un1_FF0_m0_0_bm[4]
---------------------------------------
Resource Usage Report
Part: lcmxo640c-3

Register bits: 319 of 640 (50)
I/O cells:       31

Details:
AND2:           8
BB:             8
CCU2:           21
DPR16X2B:       32
FD1P3AX:        13
FD1P3BX:        4
FD1P3DX:        188
FD1S3AX:        13
FD1S3BX:        13
FD1S3DX:        88
IB:             15
INV:            23
L6MUX21:        5
OB:             8
ORCALUT4:       362
PFUMX:          16
VHI:            1
VLO:            1
Found clock Uart4|clk with period 1000.00ns 
Found clock Uart4|clk_in with period 1000.00ns 
@W:"e:\yiluo\dd\uart4_top.v":40:5:40:6|Net baud_clk_c appears to be a clock source which was not identified. Assuming default frequency. 
@W:"e:\yiluo\dd\uart4_top.v":40:5:40:6|Net baud_clk1_c appears to be a clock source which was not identified. Assuming default frequency. 


##### START OF TIMING REPORT #####[
# Timing Report written on Fri Jul 07 14:16:33 2006
#


Top view:               Uart4
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: 492.792

                   Requested     Estimated     Requested     Estimated                 Clock        Clock              
Starting Clock     Frequency     Frequency     Period        Period        Slack       Type         Group              
-----------------------------------------------------------------------------------------------------------------------
Uart4|clk          1.0 MHz       69.4 MHz      1000.000      14.417        492.792     inferred     Inferred_clkgroup_0
Uart4|clk_in       1.0 MHz       106.3 MHz     1000.000      9.403         990.597     inferred     Inferred_clkgroup_1
System             1.0 MHz       143.4 MHz     1000.000      6.973         993.027     system       default_clkgroup   
=======================================================================================================================





Clock Relationships
*******************

Clocks                      |    rise  to  rise     |    fall  to  fall   |    rise  to  fall     |    fall  to  rise   
------------------------------------------------------------------------------------------------------------------------
Starting      Ending        |  constraint  slack    |  constraint  slack  |  constraint  slack    |  constraint  slack  
------------------------------------------------------------------------------------------------------------------------
Uart4|clk_in  Uart4|clk_in  |  1000.000    990.597  |  No paths    -      |  No paths    -        |  No paths    -      
Uart4|clk     Uart4|clk     |  1000.000    985.665  |  No paths    -      |  500.000     495.121  |  500.000     492.792
========================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

		No IO constraint found 



====================================
Detailed Report for Clock: Uart4|clk
====================================



Starting Points with Worst Slack
********************************

                     Starting                                             Arrival            
Instance             Reference     Type        Pin     Net                Time        Slack  
                     Clock                                                                   
---------------------------------------------------------------------------------------------
u12.intmask_2_.Q     Uart4|clk     FD1P3AX     Q       u12.intmask[2]     1.585       492.792
u12.intmask_4_.Q     Uart4|clk     FD1P3AX     Q       u12.intmask[4]     1.585       492.792
u12.intmask_1_.Q     Uart4|clk     FD1P3AX     Q       u12.intmask[1]     1.585       494.116
u12.intmask_3_.Q     Uart4|clk     FD1P3AX     Q       u12.intmask[3]     1.585       494.116
u12.intmask_5_.Q     Uart4|clk     FD1P3AX     Q       u12.intmask[5]     1.585       494.116
u12.intmask_6_.Q     Uart4|clk     FD1P3AX     Q       u12.intmask[6]     1.585       494.116
u12.intmask_7_.Q     Uart4|clk     FD1P3AX     Q       u12.intmask[7]     1.585       494.116
u1.A_4_.Q            Uart4|clk     FD1P3AX     Q       u1.A[4]            2.499       495.121
u1.A_0_.Q            Uart4|clk     FD1P3AX     Q       u1.A[0]            2.424       495.196
u1.A_3_.Q            Uart4|clk     FD1P3AX     Q       u1.A[3]            1.842       496.034
=============================================================================================


Ending Points with Worst Slack
******************************

                      Starting                                                              Required            
Instance              Reference     Type        Pin     Net                                 Time         Slack  
                      Clock                                                                                     
----------------------------------------------------------------------------------------------------------------
u12.int_reg.Q         Uart4|clk     FD1S3AX     D       N_51                                499.676      492.792
u12.intmask_0_.Q      Uart4|clk     FD1P3AX     SP      inter_mask                          499.676      495.121
u12.intmask_1_.Q      Uart4|clk     FD1P3AX     SP      inter_mask                          499.676      495.121
u12.intmask_2_.Q      Uart4|clk     FD1P3AX     SP      inter_mask                          499.676      495.121
u12.intmask_3_.Q      Uart4|clk     FD1P3AX     SP      inter_mask                          499.676      495.121
u12.intmask_4_.Q      Uart4|clk     FD1P3AX     SP      inter_mask                          499.676      495.121
u12.intmask_5_.Q      Uart4|clk     FD1P3AX     SP      inter_mask                          499.676      495.121
u12.intmask_6_.Q      Uart4|clk     FD1P3AX     SP      inter_mask                          499.676      495.121
u12.intmask_7_.Q      Uart4|clk     FD1P3AX     SP      inter_mask                          499.676      495.121
u10.u1.count_2_.Q     Uart4|clk     FD1S3DX     D       u10.u1.un1_count_1_cry_2_0_S0_6     999.676      985.665
================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
    Requested Period:                        500.000
    - Setup time:                            0.324
    = Required time:                         499.676

    - Propagation time:                      6.884
    = Slack (critical) :                     492.792

    Number of logic level(s):                4
    Starting point:                          u12.intmask_2_.Q / Q
    Ending point:                            u12.int_reg.Q / D
    The start point is clocked by            Uart4|clk [falling] on pin CK
    The end   point is clocked by            Uart4|clk [rising] on pin CK

Instance / Net                    Pin      Pin               Arrival     No. of    
Name                 Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------
u12.intmask_2_.Q     FD1P3AX      Q        Out     1.585     1.585       -         
u12.intmask[2]       Net          -        -       -         -           1         
u12.fifot2_int       ORCALUT4     C        In      0.000     1.585       -         
u12.fifot2_int       ORCALUT4     Z        Out     1.325     2.910       -         
u12.fifot2_int       Net          -        -       -         -           1         
u12.int_regsr_2      ORCALUT4     C        In      0.000     2.910       -         
u12.int_regsr_2      ORCALUT4     Z        Out     1.325     4.235       -         
u12.int_regsr_2      Net          -        -       -         -           1         
u12.int_regs_i       ORCALUT4     D        In      0.000     4.235       -         
u12.int_regs_i       ORCALUT4     Z        Out     1.325     5.559       -         
u12.int_regs_i       Net          -        -       -         -           1         
u12.int_reg.Q_0      ORCALUT4     A        In      0.000     5.559       -         
u12.int_reg.Q_0      ORCALUT4     Z        Out     1.325     6.884       -         
N_51                 Net          -        -       -         -           1         
u12.int_reg.Q        FD1S3AX      D        In      0.000     6.884       -         
===================================================================================




====================================
Detailed Report for Clock: Uart4|clk_in
====================================



Starting Points with Worst Slack
********************************

                        Starting                                                   Arrival            
Instance                Reference        Type        Pin     Net                   Time        Slack  
                        Clock                                                                         
------------------------------------------------------------------------------------------------------
u2.sys_clk_cnt_0_.Q     Uart4|clk_in     FD1S3DX     Q       u2.sys_clk_cnt[0]     1.880       990.597
u2.sys_clk_cnt_1_.Q     Uart4|clk_in     FD1S3DX     Q       u2.sys_clk_cnt[1]     1.842       990.635
u2.sys_clk_cnt_2_.Q     Uart4|clk_in     FD1S3DX     Q       u2.sys_clk_cnt[2]     1.842       990.846
u2.sys_clk_cnt_3_.Q     Uart4|clk_in     FD1S3DX     Q       u2.sys_clk_cnt[3]     1.842       990.846
u2.sys_clk_cnt_4_.Q     Uart4|clk_in     FD1S3DX     Q       u2.sys_clk_cnt[4]     1.842       991.057
u2.sys_clk_cnt_5_.Q     Uart4|clk_in     FD1S3DX     Q       u2.sys_clk_cnt[5]     1.842       991.057
u2.sys_clk_cnt_6_.Q     Uart4|clk_in     FD1S3DX     Q       u2.sys_clk_cnt[6]     1.880       991.230
u2.sys_clk_cnt_7_.Q     Uart4|clk_in     FD1S3DX     Q       u2.sys_clk_cnt[7]     1.880       991.230
u2.sys_clk_cnt_8_.Q     Uart4|clk_in     FD1S3BX     Q       u2.sys_clk_cnt[8]     1.880       994.058
======================================================================================================


Ending Points with Worst Slack
******************************

                        Starting                                                               Required            
Instance                Reference        Type        Pin     Net                               Time         Slack  
                        Clock                                                                                      
-------------------------------------------------------------------------------------------------------------------
u2.sys_clk_cnt_8_.Q     Uart4|clk_in     FD1S3BX     D       u2.sys_clk_cnt_5[8]               999.676      990.597
u2.sys_clk_cnt_7_.Q     Uart4|clk_in     FD1S3DX     D       u2.sys_clk_cnt_5[7]               999.676      990.808
u2.sys_clk_cnt_6_.Q     Uart4|clk_in     FD1S3DX     D       u2.un6_sys_clk_cnt_cry_6_0_S0     999.676      992.133
u2.sys_clk_cnt_4_.Q     Uart4|clk_in     FD1S3DX     D       u2.un6_sys_clk_cnt_cry_4_0_S0     999.676      992.344
u2.sys_clk_cnt_5_.Q     Uart4|clk_in     FD1S3DX     D       u2.un6_sys_clk_cnt_cry_4_0_S1     999.676      992.344
u2.sys_clk_cnt_2_.Q     Uart4|clk_in     FD1S3DX     D       u2.un6_sys_clk_cnt_cry_2_0_S0     999.676      992.555
u2.sys_clk_cnt_3_.Q     Uart4|clk_in     FD1S3DX     D       u2.un6_sys_clk_cnt_cry_2_0_S1     999.676      992.555
u2.sys_clk_cnt_1_.Q     Uart4|clk_in     FD1S3DX     D       u2.un6_sys_clk_cnt_cry_0_0_S1     999.676      995.383
u2.sys_clk_cnt_0_.Q     Uart4|clk_in     FD1S3DX     D       u2.sys_clk_cnt_i[0]               999.676      996.471