data_path.v

来自「一个UART的FPGA core」· Verilog 代码 · 共 32 行

`timescale 1ns/100ps
module data_path( 
						// output
						data,	
						// input
            EF0,AE0,AF0,FF0,EF1,AE1,AF1,FF1,
            EF2,AE2,AF2,FF2,EF3,AE3,AF3,FF3,
            EF4,AE4,AF4,FF4,EF5,AE5,AF5,FF5,
            EF6,AE6,AF6,FF6,EF7,AE7,AF7,FF7,
            datar_out0,datar_out1,datar_out2,datar_out3,
			      fifor0_cs,fifor1_cs,fifor2_cs,fifor3_cs,
			      inter_pos0,inter_pos1,inter_pos2,inter_pos3);

input EF0,AE0,AF0,FF0,EF1,AE1,AF1,FF1;
input EF2,AE2,AF2,FF2,EF3,AE3,AF3,FF3;
input EF4,AE4,AF4,FF4,EF5,AE5,AF5,FF5;
input EF6,AE6,AF6,FF6,EF7,AE7,AF7,FF7;
input [7:0] datar_out0,datar_out1,datar_out2,datar_out3;//4个读取数据
input fifor0_cs,fifor1_cs,fifor2_cs,fifor3_cs;//4个接收FIFO读取命令
input inter_pos0,inter_pos1,inter_pos2,inter_pos3;//4个中断状态位读取命令

output [7:0] data;

wire [7:0] pos0 = {EF0,AE0,AF0,FF0,EF1,AE1,AF1,FF1};
wire [7:0] pos1 = {EF2,AE2,AF2,FF2,EF3,AE3,AF3,FF3};
wire [7:0] pos2 = {EF4,AE4,AF4,FF4,EF5,AE5,AF5,FF5};
wire [7:0] pos3 = {EF6,AE6,AF6,FF6,EF7,AE7,AF7,FF7};

assign data = inter_pos0 ?  pos0 : (inter_pos1 ?  pos1 : (inter_pos2 ?  pos2 : (inter_pos3 ? pos3 : ( fifor0_cs ? datar_out0 : (fifor1_cs ? datar_out1 : (fifor2_cs ? datar_out2 : (fifor3_cs ? datar_out3 : 8'bz)))))));

endmodule