uart_fifo.v

来自「一个UART的FPGA core」· Verilog 代码 · 共 73 行

`timescale 1ns/100ps

module UART_FIFO ( clk,rst,data_in,data_out,                    // Control signals
	               push,                                           // push strobe, active high
	               pop,                                            // pop strobe, active high	 
				   EF,AE,AF,FF                                     // status signals
	             );

input clk,rst;
input push,pop;
input	[7:0] data_in;
output	[7:0] data_out;
output	EF,AE,AF,FF;

reg	[3:0] top;
reg	[3:0] bottom;
reg	[3:0] count;

wire [3:0] top_plus_1 = top + 1;

//PUR PUR_INST(.PUR(1'b1));
//GSR GSR_INST(.GSR(1'b1));

dpram16x8 u0(.WrAddress( top_plus_1 ),
             .Data( data_in ),
		 .WrClock( clk ),
		 .WE( push ), 
             .WrClockEn( push ),
		 .RdAddress( bottom ),
		  .RdClock( clk ),
		   .RdClockEn( pop ),
		  .Reset( rst ), 
             .Q( data_out ));
             

always @(posedge clk or posedge rst) // synchronous FIFO
begin
	if (rst)  	begin
		        top	<= 0 ;
		        bottom <= 1 ;
		        count <=  0;
	            end
	else        begin
	            case ({push, pop})
		        2'b10 :  if(!FF)
                                 begin
				         top  <=  top_plus_1;
				         count <= count + 1;
			             end
		        2'b01 :  if(!EF)
                                 begin
				         bottom <= bottom + 1;
				         count <= count - 1;
			             end
		        2'b11 :  begin
				         bottom <= bottom + 1;
				         top <= top_plus_1;
		                 end
                 default ;
		        endcase
	            end
end   // always

/////////////////////////////////////FLAG generator////////////////////////////////

assign FF = count[3] & count[2] & count[1] & count[0] ;
assign AF = count[3] & count[2] ;
assign AE = ~count[3] & ~count[2] ;
assign EF = ~count[3] & ~count[2] & ~count[1] & ~count[0] ;

/////////////////////////////////////////////////////////////////////////////////////////////////
endmodule