inter_tb.v

来自「一个UART的FPGA core」· Verilog 代码 · 共 23 行

module inter_tb;
 
reg clk,csn,we;
reg [4:0] addr;
reg [7:0] data;
reg inter_mask;
reg  AE0,AF0,EF0;
reg  AE1,AF1,EF1;
reg  AE2,AF2,EF2;
reg  AE3,AF3,EF3;
reg  AF4,FF4;
reg  AF5,FF5;
reg  AF6,FF6;
reg  AF7,FF7;
wire   inter;

inter u0( clk,csn,we,addr,data,
               AE0,AF0,EF0,AE1,AF1,EF1,AE2,AF2,EF2,AE3,AF3,EF3,AF4,FF4,AF5,FF5,AF6,FF6,AF7,FF7,
		       inter_mask,inter   //output
              );   

endmodule