inter.v

一个UART的FPGA core

`timescale 1ns/100ps
module  inter( clk,csn,we,addr,data,
               AE0,AF0,EF0,AE1,AF1,EF1,AE2,AF2,EF2,AE3,AF3,EF3,AF4,FF4,AF5,FF5,AF6,FF6,AF7,FF7,
		       inter_mask,inter   //output
              );             
 
input clk,csn,we;
input [4:0] addr;
input [7:0] data;
input inter_mask;
input  AE0,AF0,EF0;
input  AE1,AF1,EF1;
input  AE2,AF2,EF2;
input  AE3,AF3,EF3;
input  AF4,FF4;
input  AF5,FF5;
input  AF6,FF6;
input  AF7,FF7;
output   inter;

reg [7:0] intmask;
wire fifor0_int,fifor1_int,fifor2_int,fifor3_int;
wire fifot0_int,fifot1_int,fifot2_int,fifot3_int;

always @(negedge clk )    if (inter_mask) intmask <= data;				

assign    fifor0_int =  (FF4 | AF4) & intmask[4];
assign    fifor1_int=  (FF5 | AF5) & intmask[5];
assign    fifor2_int = (FF6 | AF6) & intmask[6];
assign    fifor3_int = (FF7 | AF7) & intmask[7];
assign    fifot0_int =  (EF0 | AE0 | AF0) & intmask[0];
assign    fifot1_int =  (EF1 | AE1 | AF1) & intmask[1];
assign    fifot2_int = (EF2 | AE2 | AF2) & intmask[2];
assign    fifot3_int =  (EF3 | AE3 | AF3) & intmask[3];
  
reg int_reg;
always @(posedge clk)
int_reg <= (fifor0_int |fifor1_int |fifor2_int |fifor3_int |fifot0_int |fifot1_int | fifot2_int | fifot3_int) ; 

assign inter = ~int_reg; 

endmodule