txmit.v

一个UART的FPGA core

`timescale 1 ns / 100ps

module txmit ( clk,clk_in,rst,data,we,baud_clk,
               sdo,EF,AE,AF,FF,we_en
               ) ;  //发送模块

output sdo ;//serial data output
output EF,AE,AF,FF; 
input [7:0] data;
input clk , rst,clk_in ;
input we ;  //FIFO片选信号
input baud_clk;   //串口传送波特率时钟
output we_en;

//reg tsre ; //标志位，标志tsr为空
//reg baud_clk_enable;
wire [7:0] tsr_tmp ; //作移位输出到SDO使用
reg [7:0] tsr;

reg sdo ;

reg [3:0] no_bits_sent ;   //控制串出数据顺序

//wire [7:0] q;
reg rd;
wire  EF,AE,AF,FF;

reg tmp; //[2:0] tmp;
reg we_en;
reg tmp1;
always @(posedge clk) begin
                      tmp = we ; //tmp <= tmp + 1 ;
                      end

always @(posedge clk) begin
                      tmp1 = tmp; //tmp <= tmp + 1 ;
                      end

always @(posedge clk) begin
                      we_en = !FF & !we & tmp1;
                      end

//always @(posedge tmp[1]) tmp1 <= we ;


//we_en = !FF & !we & tmp1;

UART_FIFO u0( .clk( clk ),
              .rst( rst ),
              .data_in( data ),
	      .data_out( tsr_tmp ),
	      .push( we_en ),
	      .pop( rd&!EF ),
	      .EF( EF ),
	      .AE( AE ),
	      .AF( AF ),
	      .FF( FF ));

always @(posedge baud_clk or posedge rst)
if (rst)     begin
             sdo <= 1'b1 ;
             tsr <= 8'b0 ;
             end
else   if(!EF)      begin  if(no_bits_sent == 4'b0001) tsr <= tsr_tmp;
                    else if( no_bits_sent == 4'b0010 ) sdo <= 0 ;
                    else if ((no_bits_sent >= 4'b0011) && (no_bits_sent <= 4'b1010))
                    begin
                    tsr[6:0] <= tsr[7:1] ;
                    tsr[7] <= 1'b0 ;
                    sdo <= tsr[0] ; //串出数据bit 0,bit 1,...bit 7
                    end
                    else  sdo<= 1'b1;//if (no_bits_sent == 4'b1011)  sdo <= 1'b1 ;
             end
       else sdo <= 1'b1;

reg state ;

always @(posedge clk or posedge rst)
  if(rst)   begin
            state <= 0;
            rd <= 0 ;
        end
  else  begin
           case(state)
		0 : if( (no_bits_sent == 4'b0010) && !EF ) 
		       begin
		              rd <= 1;
				  state <= 1 ;
 			  end
                1 : begin
		              rd <= 0 ;
                       if( no_bits_sent == 4'b0000) 
                              state <= 0;
		     end
            endcase
        end

always @(posedge baud_clk or posedge rst )
if (rst)    no_bits_sent <= 4'b0000 ;
else if ( ((no_bits_sent == 4'b1011) | EF) )
              no_bits_sent <= 4'b0000 ;
     else  
	         no_bits_sent <= no_bits_sent + 1 ; //第一拍，导入数据到tsr,第二拍，输出起始3，第三拍-第10拍，串出数据，第11拍，输出奇偶校验位

endmodule