uart4.edi

一个UART的FPGA core

(edif Uart4
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap (keywordLevel 0))
  (status
    (written
      (timeStamp 2006 7 7 14 16 33)
      (author "Synplicity, Inc.")
      (program "Synplify" (version "8.4.0.p, Build 020R"))
     )
   )
  (library LUCENT
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell CCU2 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port A0 (direction INPUT))
           (port B0 (direction INPUT))
           (port C0 (direction INPUT))
           (port D0 (direction INPUT))
           (port A1 (direction INPUT))
           (port B1 (direction INPUT))
           (port C1 (direction INPUT))
           (port D1 (direction INPUT))
           (port CIN (direction INPUT))
           (port COUT0 (direction OUTPUT))
           (port COUT1 (direction OUTPUT))
           (port S0 (direction OUTPUT))
           (port S1 (direction OUTPUT))
         )
       )
    )
    (cell DPR16X2B (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port RDO0 (direction OUTPUT))
           (port RDO1 (direction OUTPUT))
           (port WDO0 (direction OUTPUT))
           (port WDO1 (direction OUTPUT))
           (port RAD0 (direction INPUT))
           (port RAD1 (direction INPUT))
           (port RAD2 (direction INPUT))
           (port RAD3 (direction INPUT))
           (port WAD0 (direction INPUT))
           (port WAD1 (direction INPUT))
           (port WAD2 (direction INPUT))
           (port WAD3 (direction INPUT))
           (port DI0 (direction INPUT))
           (port DI1 (direction INPUT))
           (port WRE (direction INPUT))
           (port WCK (direction INPUT))
         )
        (property initval (integer 0))
       )
    )
    (cell BB (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port B (direction INOUT))
           (port I (direction INPUT))
           (port T (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell OB (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell IB (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell FD1S3DX (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port D (direction INPUT))
           (port CK (direction INPUT))
           (port CD (direction INPUT))
           (port Q (direction OUTPUT))
         )
       )
    )
    (cell FD1S3BX (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port D (direction INPUT))
           (port CK (direction INPUT))
           (port PD (direction INPUT))
           (port Q (direction OUTPUT))
         )
       )
    )
    (cell FD1S3AX (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port D (direction INPUT))
           (port CK (direction INPUT))
           (port Q (direction OUTPUT))
         )
       )
    )
    (cell FD1P3DX (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port D (direction INPUT))
           (port SP (direction INPUT))
           (port CK (direction INPUT))
           (port CD (direction INPUT))
           (port Q (direction OUTPUT))
         )
       )
    )
    (cell FD1P3BX (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port D (direction INPUT))
           (port SP (direction INPUT))
           (port CK (direction INPUT))
           (port PD (direction INPUT))
           (port Q (direction OUTPUT))
         )
       )
    )
    (cell FD1P3AX (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port D (direction INPUT))
           (port SP (direction INPUT))
           (port CK (direction INPUT))
           (port Q (direction OUTPUT))
         )
       )
    )
    (cell AND2 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port A (direction INPUT))
           (port B (direction INPUT))
           (port Z (direction OUTPUT))
         )
       )
    )
    (cell ORCALUT4 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port A (direction INPUT))
           (port B (direction INPUT))
           (port C (direction INPUT))
           (port D (direction INPUT))
           (port Z (direction OUTPUT))
         )
       )
    )
    (cell L6MUX21 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port D1 (direction INPUT))
           (port D0 (direction INPUT))
           (port SD (direction INPUT))
           (port Z (direction OUTPUT))
         )
       )
    )
    (cell PFUMX (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port ALUT (direction INPUT))
           (port BLUT (direction INPUT))
           (port C0 (direction INPUT))
           (port Z (direction OUTPUT))
         )
       )
    )
    (cell PUR (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port PUR (direction INPUT))
         )
       )
    )
    (cell GSR (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port GSR (direction INPUT))
         )
       )
    )
    (cell INV (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port A (direction INPUT))
           (port Z (direction OUTPUT))
         )
       )
    )
    (cell VHI (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Z (direction OUTPUT))
         )
       )
    )
    (cell VLO (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Z (direction OUTPUT))
         )
       )
    )
  )
  (library work
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell dpram16x8_7_1 (cellType GENERIC)
       (view netlist (viewType NETLIST)
         (interface
           (port (array (rename datar_out3 "datar_out3[7:0]") 8) (direction OUTPUT))
           (port (array (rename rsr "rsr[7:0]") 8) (direction INPUT))
           (port (array (rename top_i "top_i[0:0]") 1) (direction INPUT))
           (port (array (rename bottom "bottom[3:0]") 4) (direction INPUT))
           (port wr (direction INPUT))
           (port VCC (direction INPUT))
           (port rst_c (direction INPUT))
           (port pop (direction INPUT))
           (port GND (direction INPUT))
           (port clk_c (direction INPUT))
           (port un1_top_axbxc3_6 (direction INPUT))
           (port un1_top_axbxc2_6 (direction INPUT))
           (port un1_top_axbxc1_6 (direction INPUT))
         )
         (contents
          (instance mem_0_3 (viewRef PRIM (cellRef DPR16X2B (libraryRef LUCENT)))
           (property initval (string "0x0000000000000000"))
          )
          (instance mem_0_2 (viewRef PRIM (cellRef DPR16X2B (libraryRef LUCENT)))
           (property initval (string "0x0000000000000000"))
          )
          (instance mem_0_1 (viewRef PRIM (cellRef DPR16X2B (libraryRef LUCENT)))
           (property initval (string "0x0000000000000000"))
          )
          (instance mem_0_0 (viewRef PRIM (cellRef DPR16X2B (libraryRef LUCENT)))
           (property initval (string "0x0000000000000000"))
          )
          (instance FF_0 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
          )
          (instance FF_1 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
          )
          (instance FF_2 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
          )
          (instance FF_3 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
          )
          (instance FF_4 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
          )
          (instance FF_5 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
          )
          (instance FF_6 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
          )
          (instance FF_7 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT)))
          )
          (instance AND2_t0 (viewRef PRIM (cellRef AND2 (libraryRef LUCENT)))
          )
          (net WDO0_27 (joined
           (portRef WDO0 (instanceRef mem_0_3))
          ))
          (net WDO1_27 (joined
           (portRef WDO1 (instanceRef mem_0_3))
          ))
          (net rsr_0 (joined
           (portRef (member rsr 7))
           (portRef DI0 (instanceRef mem_0_3))
          ))
          (net rsr_1 (joined
           (portRef (member rsr 6))
           (portRef DI1 (instanceRef mem_0_3))
          ))
          (net WDO0_28 (joined
           (portRef WDO0 (instanceRef mem_0_2))
          ))
          (net WDO1_28 (joined
           (portRef WDO1 (instanceRef mem_0_2))
          ))
          (net rsr_2 (joined
           (portRef (member rsr 5))
           (portRef DI0 (instanceRef mem_0_2))
          ))
          (net rsr_3 (joined
           (portRef (member rsr 4))
           (portRef DI1 (instanceRef mem_0_2))
          ))
          (net WDO0_29 (joined
           (portRef WDO0 (instanceRef mem_0_1))
          ))
          (net WDO1_29 (joined
           (portRef WDO1 (instanceRef mem_0_1))
          ))
          (net rsr_4 (joined
           (portRef (member rsr 3))
           (portRef DI0 (instanceRef mem_0_1))
          ))
          (net rsr_5 (joined
           (portRef (member rsr 2))
           (portRef DI1 (instanceRef mem_0_1))
          ))
          (net WDO0_30 (joined
           (portRef WDO0 (instanceRef mem_0_0))
          ))
          (net WDO1_30 (joined
           (portRef WDO1 (instanceRef mem_0_0))
          ))
          (net bottom_0 (joined
           (portRef (member bottom 3))
           (portRef RAD0 (instanceRef mem_0_3))
           (portRef RAD0 (instanceRef mem_0_2))
           (portRef RAD0 (instanceRef mem_0_1))
           (portRef RAD0 (instanceRef mem_0_0))
          ))
          (net bottom_1 (joined
           (portRef (member bottom 2))
           (portRef RAD1 (instanceRef mem_0_3))
           (portRef RAD1 (instanceRef mem_0_2))
           (portRef RAD1 (instanceRef mem_0_1))
           (portRef RAD1 (instanceRef mem_0_0))
          ))
          (net bottom_2 (joined
           (portRef (member bottom 1))
           (portRef RAD2 (instanceRef mem_0_3))
           (portRef RAD2 (instanceRef mem_0_2))
           (portRef RAD2 (instanceRef mem_0_1))
           (portRef RAD2 (instanceRef mem_0_0))
          ))
          (net bottom_3 (joined
           (portRef (member bottom 0))
           (portRef RAD3 (instanceRef mem_0_3))
           (portRef RAD3 (instanceRef mem_0_2))
           (portRef RAD3 (instanceRef mem_0_1))
           (portRef RAD3 (instanceRef mem_0_0))
          ))
          (net top_i_0 (joined
           (portRef (member top_i 0))
           (portRef WAD0 (instanceRef mem_0_3))
           (portRef WAD0 (instanceRef mem_0_2))
           (portRef WAD0 (instanceRef mem_0_1))
           (portRef WAD0 (instanceRef mem_0_0))
          ))
          (net un1_top_axbxc1_6 (joined
           (portRef un1_top_axbxc1_6)
           (portRef WAD1 (instanceRef mem_0_3))