dpram16x8.v

一个UART的FPGA core

/* Verilog netlist generated by SCUBA ispLever_v51_Prod_Build (38) */
/* Module Version: 2.0 */
/* d:\ispTOOLS5_1\ispfpga\bin\nt\scuba.exe -w -lang verilog -synth synplify -bus_exp 7 -bb -arch mj5g00 -type sdpram -rdata_width 8 -data_width 8 -num_rows 16 -outData REGISTERED -e  */
/* Thu Jan 05 15:34:00 2006 */


`timescale 1 ns / 1 ps
module dpram16x8 (WrAddress, Data, WrClock, WE, WrClockEn, RdAddress, 
    RdClock, RdClockEn, Reset, Q);
    input [3:0] WrAddress;
    input [7:0] Data;
    input WrClock;
    input WE;
    input WrClockEn;
    input [3:0] RdAddress;
    input RdClock;
    input RdClockEn;
    input Reset;
    output [7:0] Q;


    AND2 AND2_t0 (.A(WE), .B(WrClockEn), .Z(dec_wre3));

    FD1P3DX FF_7 (.D(dataout7_ffin), .SP(RdClockEn), .CK(RdClock), .CD(Reset), 
        .Q(Q[7]));

    FD1P3DX FF_6 (.D(dataout6_ffin), .SP(RdClockEn), .CK(RdClock), .CD(Reset), 
        .Q(Q[6]));

    FD1P3DX FF_5 (.D(dataout5_ffin), .SP(RdClockEn), .CK(RdClock), .CD(Reset), 
        .Q(Q[5]));

    FD1P3DX FF_4 (.D(dataout4_ffin), .SP(RdClockEn), .CK(RdClock), .CD(Reset), 
        .Q(Q[4]));

    FD1P3DX FF_3 (.D(dataout3_ffin), .SP(RdClockEn), .CK(RdClock), .CD(Reset), 
        .Q(Q[3]));

    FD1P3DX FF_2 (.D(dataout2_ffin), .SP(RdClockEn), .CK(RdClock), .CD(Reset), 
        .Q(Q[2]));

    FD1P3DX FF_1 (.D(dataout1_ffin), .SP(RdClockEn), .CK(RdClock), .CD(Reset), 
        .Q(Q[1]));

    FD1P3DX FF_0 (.D(dataout0_ffin), .SP(RdClockEn), .CK(RdClock), .CD(Reset), 
        .Q(Q[0]));

    // synopsys translate_off
    defparam mem_0_0.initval =  64'h0000000000000000;
    // synopsys translate_on
    DPR16X2B mem_0_0 (.DI0(Data[6]), .DI1(Data[7]), .WCK(WrClock), .WRE(dec_wre3), 
        .RAD0(RdAddress[0]), .RAD1(RdAddress[1]), .RAD2(RdAddress[2]), .RAD3(RdAddress[3]), 
        .WAD0(WrAddress[0]), .WAD1(WrAddress[1]), .WAD2(WrAddress[2]), .WAD3(WrAddress[3]), 
        .WDO0(), .WDO1(), .RDO0(dataout6_ffin), .RDO1(dataout7_ffin))
             /* synthesis initval="0x0000000000000000" */;

    // synopsys translate_off
    defparam mem_0_1.initval =  64'h0000000000000000;
    // synopsys translate_on
    DPR16X2B mem_0_1 (.DI0(Data[4]), .DI1(Data[5]), .WCK(WrClock), .WRE(dec_wre3), 
        .RAD0(RdAddress[0]), .RAD1(RdAddress[1]), .RAD2(RdAddress[2]), .RAD3(RdAddress[3]), 
        .WAD0(WrAddress[0]), .WAD1(WrAddress[1]), .WAD2(WrAddress[2]), .WAD3(WrAddress[3]), 
        .WDO0(), .WDO1(), .RDO0(dataout4_ffin), .RDO1(dataout5_ffin))
             /* synthesis initval="0x0000000000000000" */;

    // synopsys translate_off
    defparam mem_0_2.initval =  64'h0000000000000000;
    // synopsys translate_on
    DPR16X2B mem_0_2 (.DI0(Data[2]), .DI1(Data[3]), .WCK(WrClock), .WRE(dec_wre3), 
        .RAD0(RdAddress[0]), .RAD1(RdAddress[1]), .RAD2(RdAddress[2]), .RAD3(RdAddress[3]), 
        .WAD0(WrAddress[0]), .WAD1(WrAddress[1]), .WAD2(WrAddress[2]), .WAD3(WrAddress[3]), 
        .WDO0(), .WDO1(), .RDO0(dataout2_ffin), .RDO1(dataout3_ffin))
             /* synthesis initval="0x0000000000000000" */;

    // synopsys translate_off
    defparam mem_0_3.initval =  64'h0000000000000000;
    // synopsys translate_on
    DPR16X2B mem_0_3 (.DI0(Data[0]), .DI1(Data[1]), .WCK(WrClock), .WRE(dec_wre3), 
        .RAD0(RdAddress[0]), .RAD1(RdAddress[1]), .RAD2(RdAddress[2]), .RAD3(RdAddress[3]), 
        .WAD0(WrAddress[0]), .WAD1(WrAddress[1]), .WAD2(WrAddress[2]), .WAD3(WrAddress[3]), 
        .WDO0(), .WDO1(), .RDO0(dataout0_ffin), .RDO1(dataout1_ffin))
             /* synthesis initval="0x0000000000000000" */;



    // exemplar begin
    // exemplar attribute mem_0_0 initval 0x0000000000000000
    // exemplar attribute mem_0_1 initval 0x0000000000000000
    // exemplar attribute mem_0_2 initval 0x0000000000000000
    // exemplar attribute mem_0_3 initval 0x0000000000000000
    // exemplar end

endmodule