5_1.par

一个UART的FPGA core

Lattice Place and Route Report for Design "uart_map.ncd"
Fri Jul 07 14:17:03 2006

PAR: Place And Route ispLever_v51_Prod_Build (38).
Command line: d:/ispTOOLS5_1/ispfpga\bin\nt\par -f uart.p2t uart_map.ncd uart.dir uart.prf
Preference file: uart.prf.
Placement level-cost: 5-1.
Routing Iterations: 6

Loading design for application par from file uart_map.ncd.
   "Uart4" is an NCD, version 3.0, vendor LATTICE, device LCMXO640C,
package TQFP144, speed 3
Loading device for application par from file 'mj5g12x10.nph' in environment
d:/ispTOOLS5_1/ispfpga.
Package: Version 1.13, Status: FINAL
Speed Hardware Data: version 9.999


Ignore Preference Error(s):  Yes
Dumping design to file C:/DOCUME~1/alex/LOCALS~1/Temp/neo_2.
Device utilization summary:


   PIO               31/160          19% used
                     31/113          27% bonded

   SLICE            283/320          88% used



Number of Signals: 819
Number of Connections: 2824
WARNING - par: Secondary clock driver 'rst' is located at 76 (not a
          dedicated clock PIO). Please check if user already located this
          comp, or this comp has dedicated connection with PLLs which must
          be placed at its corresponding dedicated PIOs. 
No signal is selected as Global Set/Reset.
Starting Placer Phase 0.
.............
Finished Placer Phase 0.  REAL time: 3 secs 

Starting Placer Phase 1.
Placer score = 2393992.
..........................
Placer score = 392948.
Finished Placer Phase 1.  REAL time: 1 mins 40 secs 

Starting Placer Phase 2.
.
Placer score =  388348
Finished Placer Phase 2.  REAL time: 1 mins 42 secs 


------------------ Clock Report ------------------

Global Clock Resources:
  CLK_PIN    : 2 out of 4 (50%)
  General PIO: 1 out of 160 (0%)

Global Clocks:
  PRIMARY "clk_c" from CLK_PIN "58", driver "clk", clk load = 165
  PRIMARY "baud_clk1_c" from ROUTING "R2C7A.F0", driver "u2/SLICE_320", clk load = 16
  PRIMARY "baud_clk_c" from ROUTING "R4C2B.OFX0", driver "SLICE_245", clk load = 36
  PRIMARY "clk_in_c" from CLK_PIN "55", driver "clk_in", clk load = 5
  SECONDARY "rst_c" from PIO "76", driver "rst", clk load = 0, ce load = 0, sr load = 166

  PRIMARY  : 4 out of 4 (100%)
  SECONDARY: 1 out of 4 (25%)

--------------- End of Clock Report ---------------


Total placer CPU time: 1 mins 39 secs 

Dumping design to file uart.dir/5_1.ncd.

0 connections routed; 2824 unrouted.
Starting router resource preassignment
Clock Skew Minimization: OFF
WARNING - par: The driver of secondary clock net rst_c is not placed on one
          of the PIO sites which are dedicated for secondary clocks.  This
          secondary clock will be routed through general routing resource
          and may suffer from excessive delay or skew.
Completed router resource preassignment. Real time: 1 mins 44 secs 
Starting iterative routing.

For each routing iteration the number inside the parenthesis is the
total time (in picoseconds) the design is failing the timing constraints.
For each routing iteration the router will attempt to reduce this number
until the number of routing iterations is completed or the value is 0
meaning the design has fully met the timing constraints.

End of iteration 1
2824 successful; 0 unrouted; (0) real time: 1 mins 45 secs 
Dumping design to file uart.dir/5_1.ncd.

Holding_time iterations:
Total CPU time 1 mins 42 secs 
Total REAL time: 1 mins 45 secs 
Completely routed.
End of route.  2824 routed (100.00%); 0 unrouted.
Checking DRC ... 
No errors found.
Timing score: 0 

Total REAL time to completion: 1 mins 46 secs 


All signals are completely routed.


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