uart.lci

一个UART的FPGA core

[Device]
Family = mj5g00;
PartNumber = LCMXO640C-3T144CES;
Package = TQFP144;
PartType = LCMXO640C;
Speed = -3;
Operating_condition = COM;
Status = Production;

[Revision]
Parent = mj5g00.lci;
DATE = 2002;
TIME = 0:00:00;
Source_Format = Schematic_Verilog_HDL;
Synthesis = Synplify;

[Ignore Assignments]

[Clear Assignments]

[Backannotate Assignments]

[Global Constraints]

[Location Assignments]
layer = OFF;

[Group Assignments]
layer = OFF;

[Resource Reservations]
layer = OFF;

[Fitter Report Format]

[Power]

[Source Constraint Option]

[Fast Bypass]

[OSM Bypass]

[Input Registers]

[Netlist/Delay Format]
NetList = VERILOG;

[IO Types]
layer = OFF;

[Pullup]

[Slewrate]

[Region]

[Timing Constraints]

[HSI Attributes]

[Input Delay]

[opt global constraints list]

[Explorer User Settings]

[Pin attributes list]

[global constraints list]

[Global Constraints Process Update]

[pin lock limitation]

[LOCATION ASSIGNMENTS LIST]

[RESOURCE RESERVATIONS LIST]

[individual constraints list]

[Attributes list setting]

[Timing Analyzer]

[PLL Assignments]

[Dual Function Macrocell]

[Explorer Results]

[VHDL synplify constraints]

[VHDL spectrum constraints]

[verilog synplify constraints]

[verilog spectrum constraints]

[VHDL synplify constraints list]

[VHDL spectrum constraints list]

[verilog synplify constraints list]

[verilog spectrum constraints list]

[Explorer Run Settings]