uart4.vm

一个UART的FPGA core

  FD1S3AX \tmp.Q_Z  (
	.D(Q_0_1),
	.CK(clk_c),
	.Q(tmp),
	.QN(Q_QN_21),
	.GSR(VCC)
);
// @11:78
  FD1S3DX \state.Q_Z  (
	.D(state_7),
	.CK(clk_c),
	.CD(rst_c),
	.Q(state),
	.QN(Q_QN_22),
	.GSR(VCC)
);
// @11:59
  FD1P3BX \sdo.Q_Z  (
	.D(sdo_8),
	.SP(tsr_0_sqmuxa_i),
	.CK(baud_clk_c),
	.PD(rst_c),
	.Q(txd_c[0]),
	.QN(Q_QN_23),
	.GSR(VCC)
);
// @11:78
  FD1P3DX \rd.Q_Z  (
	.D(state_i),
	.SP(rd_1_sqmuxa_i),
	.CK(clk_c),
	.CD(rst_c),
	.Q(rd),
	.QN(Q_QN_24),
	.GSR(VCC)
);
// @11:98
  FD1S3DX \no_bits_sent_3_.Q_Z  (
	.D(no_bits_sent_n3),
	.CK(baud_clk_c),
	.CD(rst_c),
	.Q(no_bits_sent[3]),
	.QN(Q_QN_25),
	.GSR(VCC)
);
// @11:98
  FD1S3DX \no_bits_sent_2_.Q_Z  (
	.D(no_bits_sent_n2),
	.CK(baud_clk_c),
	.CD(rst_c),
	.Q(no_bits_sent[2]),
	.QN(Q_QN_26),
	.GSR(VCC)
);
// @11:98
  FD1S3DX \no_bits_sent_1_.Q_Z  (
	.D(no_bits_sent_n1),
	.CK(baud_clk_c),
	.CD(rst_c),
	.Q(no_bits_sent[1]),
	.QN(Q_QN_27),
	.GSR(VCC)
);
// @11:98
  FD1S3DX \no_bits_sent_0_.Q_Z  (
	.D(no_bits_sent_n0),
	.CK(baud_clk_c),
	.CD(rst_c),
	.Q(no_bits_sent[0]),
	.QN(Q_QN_28),
	.GSR(VCC)
);
assign tsr16 = (no_bits_sent[0] & no_bits_sent[1] & ~no_bits_sent[3]) | 
   (no_bits_sent[0] & no_bits_sent[1] & ~no_bits_sent[2] & ~no_bits_sent[3]) | 
   (no_bits_sent[2] & ~no_bits_sent[3]) | (~no_bits_sent[0] & ~no_bits_sent[2] & 
   no_bits_sent[3]) | (~no_bits_sent[1] & ~no_bits_sent[2] & no_bits_sent[3]) | 
   (~no_bits_sent[0] & no_bits_sent[1] & ~no_bits_sent[2] & no_bits_sent[3]);
assign tsr_7[0] = (~tsr14 & tsr[1]) | (~tsr14 & tsr[1] & ~tsr_tmp[0]) | 
   (tsr14 & tsr_tmp[0]) | (tsr14 & ~tsr[1] & tsr_tmp[0]) | (tsr[1] & tsr_tmp[0]);
assign tsr_7[1] = (~tsr14 & tsr[2]) | (~tsr14 & tsr[2] & ~tsr_tmp[1]) | 
   (tsr14 & tsr_tmp[1]) | (tsr14 & ~tsr[2] & tsr_tmp[1]) | (tsr[2] & tsr_tmp[1]);
assign tsr_7[2] = (~tsr14 & tsr[3]) | (~tsr14 & tsr[3] & ~tsr_tmp[2]) | 
   (tsr14 & tsr_tmp[2]) | (tsr14 & ~tsr[3] & tsr_tmp[2]) | (tsr[3] & tsr_tmp[2]);
assign tsr_7[3] = (~tsr14 & tsr[4]) | (~tsr14 & tsr[4] & ~tsr_tmp[3]) | 
   (tsr14 & tsr_tmp[3]) | (tsr14 & ~tsr[4] & tsr_tmp[3]) | (tsr[4] & tsr_tmp[3]);
assign tsr_7[4] = (~tsr14 & tsr[5]) | (~tsr14 & tsr[5] & ~tsr_tmp[4]) | 
   (tsr14 & tsr_tmp[4]) | (tsr14 & ~tsr[5] & tsr_tmp[4]) | (tsr[5] & tsr_tmp[4]);
assign tsr_7[5] = (~tsr14 & tsr[6]) | (~tsr14 & tsr[6] & ~tsr_tmp[5]) | 
   (tsr14 & tsr_tmp[5]) | (tsr14 & ~tsr[6] & tsr_tmp[5]) | (tsr[6] & tsr_tmp[5]);
assign tsr_7[6] = (~tsr14 & tsr[7]) | (~tsr14 & tsr[7] & ~tsr_tmp[6]) | 
   (tsr14 & tsr_tmp[6]) | (tsr14 & ~tsr[7] & tsr_tmp[6]) | (tsr[7] & tsr_tmp[6]);
assign tsr_7[7] = (tsr14 & tsr_tmp[7]);
assign no_bits_sent_n0 = (no_bits_sent17_i & ~no_bits_sent[0]);
assign no_bits_sent_n1 = (no_bits_sent17_i & no_bits_sent[0] & ~no_bits_sent[1]) | 
   (no_bits_sent17_i & ~no_bits_sent[0] & no_bits_sent[1]);
assign no_bits_sent_n3 = (~EF0 & no_bits_sent[3] & ~no_bits_sent_c1) | 
   (~EF0 & no_bits_sent[2] & ~no_bits_sent[3] & no_bits_sent_c1);
assign state_7 = (sdo_1_sqmuxa & ~state) | (sdo_1_sqmuxa & ~state19) | 
   (sdo_1_sqmuxa & ~state & ~state19) | (state & ~state19) | (sdo_1_sqmuxa & 
   ~state & state19);
assign un1_EF_2 = (~EF0 & tsr14 & ~tsr15) | (~EF0 & tsr14 & ~tsr15 & ~tsr16) | 
   (~EF0 & ~tsr15 & tsr16);
assign tmpc = (~A_1 & A_4 & N_63 & N_65);
assign no_bits_sent17_i = (~EF0 & no_bits_sent[2]) | (~EF0 & ~no_bits_sent[3]) | 
   (~EF0 & no_bits_sent[2] & no_bits_sent[3]) | (~EF0 & ~no_bits_sent_c1) | 
   (~EF0 & no_bits_sent[2] & no_bits_sent_c1) | (~EF0 & ~no_bits_sent[3] & 
   no_bits_sent_c1) | (~EF0 & no_bits_sent[2] & no_bits_sent[3] & no_bits_sent_c1);
assign state19 = (~no_bits_sent[0] & ~no_bits_sent[1] & ~no_bits_sent[2] & 
   ~no_bits_sent[3]);
assign tsr15 = (~no_bits_sent[0] & no_bits_sent[1] & ~no_bits_sent[2] & 
   ~no_bits_sent[3]);
assign tsr14 = (no_bits_sent[0] & ~no_bits_sent[1] & ~no_bits_sent[2] & 
   ~no_bits_sent[3]);
assign no_bits_sent_c1 = (no_bits_sent[0] & no_bits_sent[1]);
// @11:48
  UART_FIFO_8 u0 (
	.data_in({data_in[7], data_in[6], data_in[5], data_in[4], data_in[3], 
   data_in[2], data_in[1], data_in[0]}),
	.tsr_tmp({tsr_tmp[7], tsr_tmp[6], tsr_tmp[5], tsr_tmp[4], tsr_tmp[3], 
   tsr_tmp[2], tsr_tmp[1], tsr_tmp[0]}),
	.count({count[3], count[2], count[1], count[0]}),
	.AE0(AE0),
	.rd(rd),
	.GND(GND),
	.VCC(VCC),
	.rst_c(rst_c),
	.clk_c(clk_c),
	.FF0(FF0),
	.un1_EF_1(un1_EF_1),
	.we_en1_c(we_en1_c),
	.EF0(EF0)
);
//@2:1
  assign NN_1 = 1'b0;
//@2:1
  assign NN_2 = 1'b1;
endmodule /* txmit_u3_4 */

module dpram16x8_1_1 (
  tsr_tmp,
  data_in,
  top_i,
  bottom,
  we_en2,
  VCC,
  rst_c,
  un1_EF_1_0,
  GND,
  clk_c,
  un1_top_axbxc3_0,
  un1_top_axbxc2_0,
  un1_top_axbxc1_0
);
output [7:0] tsr_tmp ;
input [7:0] data_in ;
input [0:0] top_i ;
input [3:0] bottom ;
input we_en2 ;
input VCC ;
input rst_c ;
input un1_EF_1_0 ;
input GND ;
input clk_c ;
input un1_top_axbxc3_0 ;
input un1_top_axbxc2_0 ;
input un1_top_axbxc1_0 ;
wire we_en2 ;
wire VCC ;
wire rst_c ;
wire un1_EF_1_0 ;
wire GND ;
wire clk_c ;
wire un1_top_axbxc3_0 ;
wire un1_top_axbxc2_0 ;
wire un1_top_axbxc1_0 ;
wire WDO0_3 ;
wire WDO1_3 ;
wire WDO0_4 ;
wire WDO1_4 ;
wire WDO0_5 ;
wire WDO1_5 ;
wire WDO0_6 ;
wire WDO1_6 ;
wire dataout0_ffin ;
wire FF_0_QN_0 ;
wire dataout1_ffin ;
wire FF_1_QN_0 ;
wire dataout2_ffin ;
wire FF_2_QN_0 ;
wire dataout3_ffin ;
wire FF_3_QN_0 ;
wire dataout4_ffin ;
wire FF_4_QN_0 ;
wire dataout5_ffin ;
wire FF_5_QN_0 ;
wire dataout6_ffin ;
wire FF_6_QN_0 ;
wire dataout7_ffin ;
wire FF_7_QN_0 ;
wire dec_wre3 ;
wire NN_1 ;
wire NN_2 ;
// @9:24
  DPR16X2B mem_0_3_Z (
	.RDO0(dataout0_ffin),
	.RDO1(dataout1_ffin),
	.WDO0(WDO0_3),
	.WDO1(WDO1_3),
	.RAD0(bottom[0]),
	.RAD1(bottom[1]),
	.RAD2(bottom[2]),
	.RAD3(bottom[3]),
	.WAD0(top_i[0]),
	.WAD1(un1_top_axbxc1_0),
	.WAD2(un1_top_axbxc2_0),
	.WAD3(un1_top_axbxc3_0),
	.DI0(data_in[0]),
	.DI1(data_in[1]),
	.WRE(dec_wre3),
	.WCK(clk_c),
	.GSR(GND)
);
// @9:24
  DPR16X2B mem_0_2_Z (
	.RDO0(dataout2_ffin),
	.RDO1(dataout3_ffin),
	.WDO0(WDO0_4),
	.WDO1(WDO1_4),
	.RAD0(bottom[0]),
	.RAD1(bottom[1]),
	.RAD2(bottom[2]),
	.RAD3(bottom[3]),
	.WAD0(top_i[0]),
	.WAD1(un1_top_axbxc1_0),
	.WAD2(un1_top_axbxc2_0),
	.WAD3(un1_top_axbxc3_0),
	.DI0(data_in[2]),
	.DI1(data_in[3]),
	.WRE(dec_wre3),
	.WCK(clk_c),
	.GSR(GND)
);
// @9:24
  DPR16X2B mem_0_1_Z (
	.RDO0(dataout4_ffin),
	.RDO1(dataout5_ffin),
	.WDO0(WDO0_5),
	.WDO1(WDO1_5),
	.RAD0(bottom[0]),
	.RAD1(bottom[1]),
	.RAD2(bottom[2]),
	.RAD3(bottom[3]),
	.WAD0(top_i[0]),
	.WAD1(un1_top_axbxc1_0),
	.WAD2(un1_top_axbxc2_0),
	.WAD3(un1_top_axbxc3_0),
	.DI0(data_in[4]),
	.DI1(data_in[5]),
	.WRE(dec_wre3),
	.WCK(clk_c),
	.GSR(GND)
);
// @9:24
  DPR16X2B mem_0_0_Z (
	.RDO0(dataout6_ffin),
	.RDO1(dataout7_ffin),
	.WDO0(WDO0_6),
	.WDO1(WDO1_6),
	.RAD0(bottom[0]),
	.RAD1(bottom[1]),
	.RAD2(bottom[2]),
	.RAD3(bottom[3]),
	.WAD0(top_i[0]),
	.WAD1(un1_top_axbxc1_0),
	.WAD2(un1_top_axbxc2_0),
	.WAD3(un1_top_axbxc3_0),
	.DI0(data_in[6]),
	.DI1(data_in[7]),
	.WRE(dec_wre3),
	.WCK(clk_c),
	.GSR(GND)
);
// @9:24
  FD1P3DX FF_0_Z (
	.D(dataout0_ffin),
	.SP(un1_EF_1_0),
	.CK(clk_c),
	.CD(rst_c),
	.Q(tsr_tmp[0]),
	.QN(FF_0_QN_0),
	.GSR(VCC)
);
// @9:24
  FD1P3DX FF_1_Z (
	.D(dataout1_ffin),
	.SP(un1_EF_1_0),
	.CK(clk_c),
	.CD(rst_c),
	.Q(tsr_tmp[1]),
	.QN(FF_1_QN_0),
	.GSR(VCC)
);
// @9:24
  FD1P3DX FF_2_Z (
	.D(dataout2_ffin),
	.SP(un1_EF_1_0),
	.CK(clk_c),
	.CD(rst_c),
	.Q(tsr_tmp[2]),
	.QN(FF_2_QN_0),
	.GSR(VCC)
);
// @9:24
  FD1P3DX FF_3_Z (
	.D(dataout3_ffin),
	.SP(un1_EF_1_0),
	.CK(clk_c),
	.CD(rst_c),
	.Q(tsr_tmp[3]),
	.QN(FF_3_QN_0),
	.GSR(VCC)
);
// @9:24
  FD1P3DX FF_4_Z (
	.D(dataout4_ffin),
	.SP(un1_EF_1_0),
	.CK(clk_c),
	.CD(rst_c),
	.Q(tsr_tmp[4]),
	.QN(FF_4_QN_0),
	.GSR(VCC)
);
// @9:24
  FD1P3DX FF_5_Z (
	.D(dataout5_ffin),
	.SP(un1_EF_1_0),
	.CK(clk_c),
	.CD(rst_c),
	.Q(tsr_tmp[5]),
	.QN(FF_5_QN_0),
	.GSR(VCC)
);
// @9:24
  FD1P3DX FF_6_Z (
	.D(dataout6_ffin),
	.SP(un1_EF_1_0),
	.CK(clk_c),
	.CD(rst_c),
	.Q(tsr_tmp[6]),
	.QN(FF_6_QN_0),
	.GSR(VCC)
);
// @9:24
  FD1P3DX FF_7_Z (
	.D(dataout7_ffin),
	.SP(un1_EF_1_0),
	.CK(clk_c),
	.CD(rst_c),
	.Q(tsr_tmp[7]),
	.QN(FF_7_QN_0),
	.GSR(VCC)
);
// @9:24
  AND2 AND2_t0 (
	.A(we_en2),
	.B(we_en2),
	.Z(dec_wre3)
);
//@2:1
  assign NN_1 = 1'b0;
//@2:1
  assign NN_2 = 1'b1;
endmodule /* dpram16x8_1_1 */

module UART_FIFO_1_1 (
  data_in,
  tsr_tmp,
  count,
  VCC,
  rst_c,
  clk_c,
  un1_EF_1_0,
  GND,
  EF1,
  rd,
  FF1,
  we_en2
);
input [7:0] data_in ;
output [7:0] tsr_tmp ;
output [3:0] count ;
input VCC ;
input rst_c ;
input clk_c ;
input un1_EF_1_0 ;
input GND ;
input EF1 ;
input rd ;
input FF1 ;
input we_en2 ;
wire VCC ;
wire rst_c ;
wire clk_c ;
wire un1_EF_1_0 ;
wire GND ;
wire EF1 ;
wire rd ;
wire FF1 ;
wire we_en2 ;
wire [3:0] top;
wire [0:0] top_i;
wire [3:0] bottom;
wire Q_QN_30 ;
wire Q_QN_31 ;
wire N_28_i ;
wire Q_QN_32 ;
wire fb ;
wire Q_QN_33 ;
wire Q_QN_34 ;
wire Q_QN_35 ;
wire Q_QN_36 ;
wire Q_QN_37 ;
wire Q_QN_38 ;
wire Q_QN_39 ;
wire Q_QN_40 ;
wire bottom_e0 ;
wire Q_QN_41 ;
wire un1_count_1_cry_2_0_COUT0_0 ;
wire un1_count_1_cry_2_0_COUT1_0 ;
wire un1_count_1_cry_2_0_S0_0 ;
wire un1_count_1_cry_2_0_S1_0 ;
wire count_0_sqmuxa ;
wire un1_count_1_cry_0_0_COUT0_0 ;
wire un1_count_1_cry_0_0_COUT1_0 ;
wire un1_count_1_cry_0_0_S0_0 ;
wire un1_count_1_cry_0_0_S1_0 ;
wire top13 ;
wire bottom_n1 ;
wire bottom_n2 ;
wire bottom_n3 ;
wire un1_top_axbxc3_0 ;
wire un1_top_axbxc2_0 ;
wire un1_top_axbxc1_0 ;
wire NN_1 ;
wire NN_2 ;
// @2:1
  INV \top_0_.top_i[0]  (
	.A(top[0]),
	.Z(top_i[0])
);
assign count_0_sqmuxa = (we_en2 & ~FF1 & ~rd) | (we_en2 & ~FF1 & ~rd & 
   ~EF1) | (we_en2 & ~FF1 & EF1);
assign N_28_i = (we_en2 & ~FF1) | (we_en2 & ~FF1 & ~EF1) | (we_en2 & ~FF1 & 
   ~rd & ~EF1) | (we_en2 & rd & ~EF1) | (we_en2 & ~FF1 & EF1);
assign bottom_e0 = (bottom[0] & ~rd) | (bottom[0] & ~rd & ~EF1) | (~bottom[0] & 
   rd & ~EF1) | (bottom[0] & EF1);
assign fb = (top[0] & ~we_en2) | (top[0] & ~we_en2 & ~un1_EF_1_0) | (top[0] & 
   ~we_en2 & un1_EF_1_0) | (~top[0] & we_en2 & un1_EF_1_0) | (top[0] & 
   ~we_en2 & ~FF1) | (~top[0] & we_en2 & ~FF1) | (top[0] & ~we_en2 & FF1) | 
   (top[0] & ~un1_EF_1_0 & FF1) | (top[0] & ~we_en2 & un1_EF_1_0 & FF1) | 
   (~top[0] & we_en2 & un1_EF_1_0 & FF1);
// @9:36
  FD1P3DX \top_3_.Q_Z  (
	.D(un1_top_axbxc3_0),
	.SP(N_28_i),
	.CK(clk_c),
	.CD(rst_c),
	.Q(top[3]),
	.QN(Q_QN_30),
	.GSR(VCC)
);
// @9:36
  FD1P3DX \top_2_.Q_Z  (
	.D(un1_top_axbxc2_0),
	.SP(N_28_i),
	.CK(clk_c),
	.CD(rst_c),
	.Q(top[2]),
	.QN(Q_QN_31),
	.GSR(VCC)
);
// @9:36
  FD1P3DX \top_1_.Q_Z  (
	.D(un1_top_axbxc1_0),
	.SP(N_28_i),
	.CK(clk_c),
	.CD(rst_c),
	.Q(top[1]),
	.QN(Q_QN_32),
	.GSR(VCC)
);
// @9:36
  FD1S3DX \top_0_.Q_Z  (
	.D(fb),
	.CK(clk_c),
	.CD(rst_c),
	.Q(top[0]),
	.QN(Q_QN_33),
	.GSR(VCC)
);
// @9:36
  FD1S3DX \count_3_.Q_Z  (
	.D(un1_count_1_cry_2_0_S1_0),
	.CK(clk_c),
	.CD(rst_c),
	.Q(count[3]),
	.QN(Q_QN_34),
	.GSR(VCC)
);
// @9:36
  FD1S3DX \count_2_.Q_Z  (
	.D(un1_count_1_cry_2_0_S0_0),
	.CK(clk_c),
	.CD(rst_c),
	.Q(count[2]),
	.QN(Q_QN_35),
	.GSR(VCC)
);
// @9:36
  FD1S3DX \count_1_.Q_Z  (
	.D(un1_count_1_cry_0_0_S1_0),
	.CK(clk_c),
	.CD(rst_c),
	.Q(count[1]),
	.QN(Q_QN_36),
	.GSR(VCC)
);
// @9:36
  FD1S3DX \count_0_.Q_Z  (
	.D(un1_count_1_cry_0_0_S0_0),
	.CK(clk_c),
	.CD(rst_c),
	.Q(count[0]),
	.QN(Q_QN_37),
	.GSR(VCC)
);
// @9:36
  FD1P3DX \bottom_3_.Q_Z  (
	.D(bottom_n3),
	.SP(un1_EF