uart4.vm

一个UART的FPGA core

  FD1P3DX FF_7_Z (
	.D(dataout7_ffin),
	.SP(un1_EF_1),
	.CK(clk_c),
	.CD(rst_c),
	.Q(tsr_tmp[7]),
	.QN(FF_7_QN),
	.GSR(VCC)
);
// @9:24
  AND2 AND2_t0 (
	.A(we_en1_c),
	.B(we_en1_c),
	.Z(dec_wre3)
);
//@2:1
  assign NN_1 = 1'b0;
//@2:1
  assign NN_2 = 1'b1;
endmodule /* dpram16x8_8 */

module UART_FIFO_8 (
  data_in,
  tsr_tmp,
  count,
  AE0,
  rd,
  GND,
  VCC,
  rst_c,
  clk_c,
  FF0,
  un1_EF_1,
  we_en1_c,
  EF0
);
input [7:0] data_in ;
output [7:0] tsr_tmp ;
output [3:0] count ;
output AE0 ;
input rd ;
input GND ;
input VCC ;
input rst_c ;
input clk_c ;
input FF0 ;
input un1_EF_1 ;
input we_en1_c ;
output EF0 ;
wire AE0 ;
wire rd ;
wire GND ;
wire VCC ;
wire rst_c ;
wire clk_c ;
wire FF0 ;
wire un1_EF_1 ;
wire we_en1_c ;
wire EF0 ;
wire [3:0] top;
wire [0:0] top_i;
wire [3:0] bottom;
wire Q_QN_0 ;
wire Q_QN_1 ;
wire Q_QN_2 ;
wire fb ;
wire Q_QN_3 ;
wire Q_QN_4 ;
wire Q_QN_5 ;
wire Q_QN_6 ;
wire Q_QN_7 ;
wire Q_QN_8 ;
wire Q_QN_9 ;
wire Q_QN_10 ;
wire Q_QN_11 ;
wire un1_count_1_cry_2_0_COUT0 ;
wire un1_count_1_cry_2_0_COUT1 ;
wire un1_count_1_cry_2_0_S0 ;
wire un1_count_1_cry_2_0_S1 ;
wire un1_count_1_cry_0_0_COUT0 ;
wire un1_count_1_cry_0_0_COUT1 ;
wire un1_count_1_cry_0_0_S0 ;
wire un1_count_1_cry_0_0_S1 ;
wire top13 ;
wire bottom_e0 ;
wire bottom_n1 ;
wire bottom_n2 ;
wire bottom_n3 ;
wire N_28_i ;
wire count_0_sqmuxa ;
wire un1_top_axbxc3 ;
wire un1_top_axbxc2 ;
wire un1_top_axbxc1 ;
wire NN_1 ;
wire NN_2 ;
// @2:1
  INV \top_0_.top_i[0]  (
	.A(top[0]),
	.Z(top_i[0])
);
assign EF0 = (~count[1] & ~count[0] & ~count[3] & ~count[2]);
assign fb = (top[0] & ~we_en1_c) | (top[0] & ~we_en1_c & ~un1_EF_1) | (top[0] & 
   ~we_en1_c & un1_EF_1) | (~top[0] & we_en1_c & un1_EF_1) | (top[0] & 
   ~we_en1_c & ~FF0) | (~top[0] & we_en1_c & ~FF0) | (top[0] & ~we_en1_c & 
   FF0) | (top[0] & ~un1_EF_1 & FF0) | (top[0] & ~we_en1_c & un1_EF_1 & 
   FF0) | (~top[0] & we_en1_c & un1_EF_1 & FF0);
// @9:36
  FD1P3DX \top_3_.Q_Z  (
	.D(un1_top_axbxc3),
	.SP(N_28_i),
	.CK(clk_c),
	.CD(rst_c),
	.Q(top[3]),
	.QN(Q_QN_0),
	.GSR(VCC)
);
// @9:36
  FD1P3DX \top_2_.Q_Z  (
	.D(un1_top_axbxc2),
	.SP(N_28_i),
	.CK(clk_c),
	.CD(rst_c),
	.Q(top[2]),
	.QN(Q_QN_1),
	.GSR(VCC)
);
// @9:36
  FD1P3DX \top_1_.Q_Z  (
	.D(un1_top_axbxc1),
	.SP(N_28_i),
	.CK(clk_c),
	.CD(rst_c),
	.Q(top[1]),
	.QN(Q_QN_2),
	.GSR(VCC)
);
// @9:36
  FD1S3DX \top_0_.Q_Z  (
	.D(fb),
	.CK(clk_c),
	.CD(rst_c),
	.Q(top[0]),
	.QN(Q_QN_3),
	.GSR(VCC)
);
// @9:36
  FD1S3DX \count_3_.Q_Z  (
	.D(un1_count_1_cry_2_0_S1),
	.CK(clk_c),
	.CD(rst_c),
	.Q(count[3]),
	.QN(Q_QN_4),
	.GSR(VCC)
);
// @9:36
  FD1S3DX \count_2_.Q_Z  (
	.D(un1_count_1_cry_2_0_S0),
	.CK(clk_c),
	.CD(rst_c),
	.Q(count[2]),
	.QN(Q_QN_5),
	.GSR(VCC)
);
// @9:36
  FD1S3DX \count_1_.Q_Z  (
	.D(un1_count_1_cry_0_0_S1),
	.CK(clk_c),
	.CD(rst_c),
	.Q(count[1]),
	.QN(Q_QN_6),
	.GSR(VCC)
);
// @9:36
  FD1S3DX \count_0_.Q_Z  (
	.D(un1_count_1_cry_0_0_S0),
	.CK(clk_c),
	.CD(rst_c),
	.Q(count[0]),
	.QN(Q_QN_7),
	.GSR(VCC)
);
// @9:36
  FD1P3DX \bottom_3_.Q_Z  (
	.D(bottom_n3),
	.SP(un1_EF_1),
	.CK(clk_c),
	.CD(rst_c),
	.Q(bottom[3]),
	.QN(Q_QN_8),
	.GSR(VCC)
);
// @9:36
  FD1P3DX \bottom_2_.Q_Z  (
	.D(bottom_n2),
	.SP(un1_EF_1),
	.CK(clk_c),
	.CD(rst_c),
	.Q(bottom[2]),
	.QN(Q_QN_9),
	.GSR(VCC)
);
// @9:36
  FD1P3DX \bottom_1_.Q_Z  (
	.D(bottom_n1),
	.SP(un1_EF_1),
	.CK(clk_c),
	.CD(rst_c),
	.Q(bottom[1]),
	.QN(Q_QN_10),
	.GSR(VCC)
);
// @9:36
  FD1S3BX \bottom_0_.Q_Z  (
	.D(bottom_e0),
	.CK(clk_c),
	.PD(rst_c),
	.Q(bottom[0]),
	.QN(Q_QN_11),
	.GSR(VCC)
);
// @11:48
  CCU2 un1_count_1_cry_2_0 (
	.A0(count[2]),
	.B0(we_en1_c),
	.C0(un1_EF_1),
	.D0(GND),
	.A1(count[3]),
	.B1(we_en1_c),
	.C1(un1_EF_1),
	.D1(GND),
	.CIN(un1_count_1_cry_0_0_COUT1),
	.COUT0(un1_count_1_cry_2_0_COUT0),
	.COUT1(un1_count_1_cry_2_0_COUT1),
	.S0(un1_count_1_cry_2_0_S0),
	.S1(un1_count_1_cry_2_0_S1)
);
defparam un1_count_1_cry_2_0.INIT0=16'h509a;
defparam un1_count_1_cry_2_0.INIT1=16'h509a;
defparam un1_count_1_cry_2_0.INJECT1_0="NO";
defparam un1_count_1_cry_2_0.INJECT1_1="NO";
// @11:48
  CCU2 un1_count_1_cry_0_0 (
	.A0(count[0]),
	.B0(top13),
	.C0(count_0_sqmuxa),
	.D0(GND),
	.A1(count[1]),
	.B1(we_en1_c),
	.C1(un1_EF_1),
	.D1(GND),
	.CIN(GND),
	.COUT0(un1_count_1_cry_0_0_COUT0),
	.COUT1(un1_count_1_cry_0_0_COUT1),
	.S0(un1_count_1_cry_0_0_S0),
	.S1(un1_count_1_cry_0_0_S1)
);
defparam un1_count_1_cry_0_0.INIT0=16'h5056;
defparam un1_count_1_cry_0_0.INIT1=16'h509a;
defparam un1_count_1_cry_0_0.INJECT1_0="NO";
defparam un1_count_1_cry_0_0.INJECT1_1="NO";
assign top13 = (~we_en1_c & rd & ~EF0);
assign bottom_e0 = (bottom[0] & ~un1_EF_1) | (~bottom[0] & un1_EF_1);
assign bottom_n1 = (bottom[0] & ~bottom[1]) | (~bottom[0] & bottom[1]);
assign bottom_n2 = (bottom[0] & bottom[1] & ~bottom[2]) | (~bottom[0] & 
   bottom[2]) | (~bottom[1] & bottom[2]) | (~bottom[0] & bottom[1] & bottom[2]);
assign bottom_n3 = (bottom[0] & bottom[1] & bottom[2] & ~bottom[3]) | (~bottom[0] & 
   bottom[3]) | (~bottom[1] & bottom[3]) | (~bottom[0] & bottom[1] & bottom[3]) | 
   (~bottom[2] & bottom[3]) | (~bottom[0] & bottom[2] & bottom[3]) | (~bottom[1] & 
   bottom[2] & bottom[3]) | (~bottom[0] & bottom[1] & bottom[2] & bottom[3]);
assign N_28_i = (~FF0 & we_en1_c) | (~FF0 & ~un1_EF_1 & we_en1_c) | (un1_EF_1 & 
   we_en1_c);
assign count_0_sqmuxa = (~FF0 & ~un1_EF_1 & we_en1_c);
assign un1_top_axbxc3 = (top[0] & top[1] & top[2] & ~top[3]) | (~top[0] & 
   top[3]) | (~top[1] & top[3]) | (~top[0] & top[1] & top[3]) | (~top[2] & 
   top[3]) | (~top[0] & top[2] & top[3]) | (~top[1] & top[2] & top[3]) | 
   (~top[0] & top[1] & top[2] & top[3]);
assign un1_top_axbxc2 = (top[0] & top[1] & ~top[2]) | (~top[0] & top[2]) | 
   (~top[1] & top[2]) | (~top[0] & top[1] & top[2]);
assign un1_top_axbxc1 = (top[0] & ~top[1]) | (~top[0] & top[1]);
assign AE0 = (~count[2] & ~count[3]);
// @9:24
  dpram16x8_8 u0 (
	.tsr_tmp({tsr_tmp[7], tsr_tmp[6], tsr_tmp[5], tsr_tmp[4], tsr_tmp[3], 
   tsr_tmp[2], tsr_tmp[1], tsr_tmp[0]}),
	.data_in({data_in[7], data_in[6], data_in[5], data_in[4], data_in[3], 
   data_in[2], data_in[1], data_in[0]}),
	.top_i(top_i[0]),
	.bottom({bottom[3], bottom[2], bottom[1], bottom[0]}),
	.we_en1_c(we_en1_c),
	.VCC(VCC),
	.rst_c(rst_c),
	.un1_EF_1(un1_EF_1),
	.GND(GND),
	.clk_c(clk_c),
	.un1_top_axbxc3(un1_top_axbxc3),
	.un1_top_axbxc2(un1_top_axbxc2),
	.un1_top_axbxc1(un1_top_axbxc1)
);
//@2:1
  assign NN_1 = 1'b0;
//@2:1
  assign NN_2 = 1'b1;
endmodule /* UART_FIFO_8 */

module txmit_u3_4 (
  data_in,
  txd_c,
  A_1,
  A_0,
  A_4,
  count,
  N_65,
  N_63,
  rst_c,
  baud_clk_c,
  VCC,
  we_en1_c,
  clk_c,
  tmpc,
  N_72,
  FF0,
  GND,
  EF0,
  AE0
);
input [7:0] data_in ;
output [0:0] txd_c ;
input A_1 ;
input A_0 ;
input A_4 ;
output [3:0] count ;
input N_65 ;
input N_63 ;
input rst_c ;
input baud_clk_c ;
input VCC ;
output we_en1_c ;
input clk_c ;
output tmpc ;
input N_72 ;
input FF0 ;
input GND ;
output EF0 ;
output AE0 ;
wire A_1 ;
wire A_0 ;
wire A_4 ;
wire N_65 ;
wire N_63 ;
wire rst_c ;
wire baud_clk_c ;
wire VCC ;
wire we_en1_c ;
wire clk_c ;
wire tmpc ;
wire N_72 ;
wire FF0 ;
wire GND ;
wire EF0 ;
wire AE0 ;
wire [7:0] tsr;
wire [7:0] tsr_7;
wire [3:0] no_bits_sent;
wire [7:0] tsr_tmp;
wire Q_0_bm_0 ;
wire Q_0_am_0 ;
wire Q_0_0 ;
wire Q_QN ;
wire Q_QN_12 ;
wire Q_QN_13 ;
wire Q_QN_14 ;
wire Q_QN_15 ;
wire Q_QN_16 ;
wire Q_QN_17 ;
wire Q_QN_18 ;
wire Q_QN_19 ;
wire tmp1 ;
wire Q_QN_20 ;
wire Q_0_1 ;
wire tmp ;
wire Q_QN_21 ;
wire Q_QN_22 ;
wire sdo_8 ;
wire tsr_0_sqmuxa_i ;
wire Q_QN_23 ;
wire state_i ;
wire rd_1_sqmuxa_i ;
wire Q_QN_24 ;
wire Q_QN_25 ;
wire no_bits_sent_n2 ;
wire Q_QN_26 ;
wire Q_QN_27 ;
wire Q_QN_28 ;
wire no_bits_sent_n0 ;
wire no_bits_sent_n1 ;
wire no_bits_sent_n3 ;
wire sdo_1_sqmuxa ;
wire state ;
wire state_7 ;
wire tsr16 ;
wire un1_EF_2 ;
wire no_bits_sent17_i ;
wire state19 ;
wire tsr15 ;
wire tsr14 ;
wire no_bits_sent_c1 ;
wire rd ;
wire un1_EF_1 ;
wire NN_1 ;
wire NN_2 ;
// @14:47
  INV state_i_cZ (
	.A(state),
	.Z(state_i)
);
assign sdo_1_sqmuxa = (tsr15 & count[1]) | (tsr15 & count[1] & ~count[0]) | 
   (tsr15 & count[0]) | (tsr15 & ~AE0) | (tsr15 & count[1] & AE0) | (tsr15 & 
   count[1] & ~count[0] & AE0) | (tsr15 & count[0] & AE0);
assign un1_EF_1 = (rd & count[1]) | (rd & count[1] & ~count[0]) | (rd & 
   count[0]) | (rd & ~AE0) | (rd & count[1] & AE0) | (rd & count[1] & 
   ~count[0] & AE0) | (rd & count[0] & AE0);
assign tsr_0_sqmuxa_i = (~tsr14) | (~tsr14 & ~AE0) | (~tsr14 & AE0) | (~tsr14 & 
   ~count[0] & AE0) | (~count[1] & ~count[0] & AE0) | (~tsr14 & count[1] & 
   ~count[0] & AE0) | (~tsr14 & count[0] & AE0);
assign rd_1_sqmuxa_i = (state) | (state & ~EF0) | (state & ~tsr15 & ~EF0) | 
   (tsr15 & ~EF0) | (state & EF0);
assign no_bits_sent_n2 = (no_bits_sent[2] & no_bits_sent17_i & ~no_bits_sent[1]) | 
   (no_bits_sent[2] & no_bits_sent17_i & ~no_bits_sent[0]) | (no_bits_sent[2] & 
   no_bits_sent17_i & ~no_bits_sent[1] & no_bits_sent[0]) | (~no_bits_sent[2] & 
   no_bits_sent17_i & no_bits_sent[1] & no_bits_sent[0]);
assign sdo_8 = (EF0) | (tsr[0] & ~tsr15) | (~tsr16 & ~tsr15) | (tsr[0] & 
   tsr16 & ~tsr15) | (tsr[0] & ~EF0 & ~tsr15) | (~tsr16 & ~EF0 & ~tsr15) | 
   (tsr[0] & tsr16 & ~EF0 & ~tsr15) | (EF0 & ~tsr15) | (EF0 & tsr15);
// @11:39
  PFUMX \we_en.Q_0  (
	.ALUT(Q_0_bm_0),
	.BLUT(Q_0_am_0),
	.C0(tmp1),
	.Z(Q_0_0)
);
assign Q_0_bm_0 = (~FF0 & ~N_72) | (~FF0 & ~A_4) | (~FF0 & ~N_72 & A_4) | 
   (~FF0 & ~N_72 & ~A_0) | (~FF0 & ~A_4 & ~A_0) | (~FF0 & ~N_72 & A_4 & 
   ~A_0) | (~FF0 & A_0);
assign Q_0_am_0 = (GND);
assign Q_0_1 = (tmpc & ~A_0);
// @11:39
  FD1S3AX \we_en.Q_Z  (
	.D(Q_0_0),
	.CK(clk_c),
	.Q(we_en1_c),
	.QN(Q_QN),
	.GSR(VCC)
);
// @11:59
  FD1P3DX \tsr_7_.Q_Z  (
	.D(tsr_7[7]),
	.SP(un1_EF_2),
	.CK(baud_clk_c),
	.CD(rst_c),
	.Q(tsr[7]),
	.QN(Q_QN_12),
	.GSR(VCC)
);
// @11:59
  FD1P3DX \tsr_6_.Q_Z  (
	.D(tsr_7[6]),
	.SP(un1_EF_2),
	.CK(baud_clk_c),
	.CD(rst_c),
	.Q(tsr[6]),
	.QN(Q_QN_13),
	.GSR(VCC)
);
// @11:59
  FD1P3DX \tsr_5_.Q_Z  (
	.D(tsr_7[5]),
	.SP(un1_EF_2),
	.CK(baud_clk_c),
	.CD(rst_c),
	.Q(tsr[5]),
	.QN(Q_QN_14),
	.GSR(VCC)
);
// @11:59
  FD1P3DX \tsr_4_.Q_Z  (
	.D(tsr_7[4]),
	.SP(un1_EF_2),
	.CK(baud_clk_c),
	.CD(rst_c),
	.Q(tsr[4]),
	.QN(Q_QN_15),
	.GSR(VCC)
);
// @11:59
  FD1P3DX \tsr_3_.Q_Z  (
	.D(tsr_7[3]),
	.SP(un1_EF_2),
	.CK(baud_clk_c),
	.CD(rst_c),
	.Q(tsr[3]),
	.QN(Q_QN_16),
	.GSR(VCC)
);
// @11:59
  FD1P3DX \tsr_2_.Q_Z  (
	.D(tsr_7[2]),
	.SP(un1_EF_2),
	.CK(baud_clk_c),
	.CD(rst_c),
	.Q(tsr[2]),
	.QN(Q_QN_17),
	.GSR(VCC)
);
// @11:59
  FD1P3DX \tsr_1_.Q_Z  (
	.D(tsr_7[1]),
	.SP(un1_EF_2),
	.CK(baud_clk_c),
	.CD(rst_c),
	.Q(tsr[1]),
	.QN(Q_QN_18),
	.GSR(VCC)
);
// @11:59
  FD1P3DX \tsr_0_.Q_Z  (
	.D(tsr_7[0]),
	.SP(un1_EF_2),
	.CK(baud_clk_c),
	.CD(rst_c),
	.Q(tsr[0]),
	.QN(Q_QN_19),
	.GSR(VCC)
);
// @11:35
  FD1S3AX \tmp1.Q_Z  (
	.D(tmp),
	.CK(clk_c),
	.Q(tmp1),
	.QN(Q_QN_20),
	.GSR(VCC)
);
// @11:31