uart4.vm

一个UART的FPGA core

  assign #(1)  un1_RAD0b_8 = RAD0b  & RAD1b  & RAD3b  & un1_RAD2b ;
  assign #(1)  un1_RAD2b_2 = RAD2b  & RAD3b  & un1_RAD0b  & un1_RAD1b ;
  assign #(1)  un1_RAD0b_9 = RAD0b  & RAD2b  & RAD3b  & un1_RAD1b ;
  assign #(1)  un1_RAD1b_4 = RAD1b  & RAD2b  & RAD3b  & un1_RAD0b ;
  assign #(1)  un1_WAD0b_2 = un1_WAD0b  & un1_WAD1b  & un1_WAD2b  & un1_WAD3b ;
  assign #(1)  un1_WAD0b_3 = WAD0b  & un1_WAD1b  & un1_WAD2b  & un1_WAD3b ;
  assign #(1)  un1_WAD1b_1 = WAD1b  & un1_WAD0b  & un1_WAD2b  & un1_WAD3b ;
  assign #(1)  un1_WAD0b_4 = WAD0b  & WAD1b  & un1_WAD2b  & un1_WAD3b ;
  assign #(1)  un1_WAD2b_1 = WAD2b  & un1_WAD0b  & un1_WAD1b  & un1_WAD3b ;
  assign #(1)  un1_WAD0b_5 = WAD0b  & WAD2b  & un1_WAD1b  & un1_WAD3b ;
  assign #(1)  un1_WAD1b_2 = WAD1b  & WAD2b  & un1_WAD0b  & un1_WAD3b ;
  assign #(1)  un1_WAD0b_6 = WAD0b  & WAD1b  & WAD2b  & un1_WAD3b ;
  assign #(1)  un1_WAD3b_1 = WAD3b  & un1_WAD0b  & un1_WAD1b  & un1_WAD2b ;
  assign #(1)  un1_WAD0b_7 = WAD0b  & WAD3b  & un1_WAD1b  & un1_WAD2b ;
  assign #(1)  un1_WAD1b_3 = WAD1b  & WAD3b  & un1_WAD0b  & un1_WAD2b ;
  assign #(1)  un1_WAD0b_8 = WAD0b  & WAD1b  & WAD3b  & un1_WAD2b ;
  assign #(1)  un1_WAD2b_2 = WAD2b  & WAD3b  & un1_WAD0b  & un1_WAD1b ;
  assign #(1)  un1_WAD0b_9 = WAD0b  & WAD2b  & WAD3b  & un1_WAD1b ;
  assign #(1)  un1_WAD1b_4 = WAD1b  & WAD2b  & WAD3b  & un1_WAD0b ;
  assign #(1)  un1_MEM_15_[0] = ((!un1_wadr_reg_1 & MEM_15_[0] ) | 
	(un1_wadr_reg_1 & din_reg[0] ) | 
	(MEM_15_[0] & din_reg[0] ));
  assign #(1)  un1_MEM_15_[1] = ((!un1_wadr_reg_1 & MEM_15_[1] ) | 
	(un1_wadr_reg_1 & din_reg[1] ) | 
	(MEM_15_[1] & din_reg[1] ));
  assign #(1)  un1_MEM_5_[0] = ((!un1_wadr_reg_11 & MEM_5_[0] ) | 
	(un1_wadr_reg_11 & din_reg[0] ) | 
	(MEM_5_[0] & din_reg[0] ));
  assign #(1)  un1_MEM_5_[1] = ((!un1_wadr_reg_11 & MEM_5_[1] ) | 
	(un1_wadr_reg_11 & din_reg[1] ) | 
	(MEM_5_[1] & din_reg[1] ));
  assign #(1)  un1_MEM_9_[0] = ((!un1_wadr_reg_15 & MEM_9_[0] ) | 
	(un1_wadr_reg_15 & din_reg[0] ) | 
	(MEM_9_[0] & din_reg[0] ));
  assign #(1)  un1_MEM_9_[1] = ((!un1_wadr_reg_15 & MEM_9_[1] ) | 
	(un1_wadr_reg_15 & din_reg[1] ) | 
	(MEM_9_[1] & din_reg[1] ));
  assign #(1)  un1_MEM_11_[0] = ((!un1_wadr_reg_9 & MEM_11_[0] ) | 
	(un1_wadr_reg_9 & din_reg[0] ) | 
	(MEM_11_[0] & din_reg[0] ));
  assign #(1)  un1_MEM_11_[1] = ((!un1_wadr_reg_9 & MEM_11_[1] ) | 
	(un1_wadr_reg_9 & din_reg[1] ) | 
	(MEM_11_[1] & din_reg[1] ));
  assign #(1)  un1_MEM_0_[0] = ((!un1_wadr_reg_2 & MEM_0_[0] ) | 
	(un1_wadr_reg_2 & din_reg[0] ) | 
	(MEM_0_[0] & din_reg[0] ));
  assign #(1)  un1_MEM_0_[1] = ((!un1_wadr_reg_2 & MEM_0_[1] ) | 
	(un1_wadr_reg_2 & din_reg[1] ) | 
	(MEM_0_[1] & din_reg[1] ));
  assign #(1)  un1_MEM_12_[0] = ((!un1_wadr_reg_14 & MEM_12_[0] ) | 
	(un1_wadr_reg_14 & din_reg[0] ) | 
	(MEM_12_[0] & din_reg[0] ));
  assign #(1)  un1_MEM_12_[1] = ((!un1_wadr_reg_14 & MEM_12_[1] ) | 
	(un1_wadr_reg_14 & din_reg[1] ) | 
	(MEM_12_[1] & din_reg[1] ));
  assign #(1)  un1_MEM_14_[0] = ((!un1_wadr_reg_13 & MEM_14_[0] ) | 
	(un1_wadr_reg_13 & din_reg[0] ) | 
	(MEM_14_[0] & din_reg[0] ));
  assign #(1)  un1_MEM_14_[1] = ((!un1_wadr_reg_13 & MEM_14_[1] ) | 
	(un1_wadr_reg_13 & din_reg[1] ) | 
	(MEM_14_[1] & din_reg[1] ));
  assign #(1)  un1_MEM_10_[0] = ((!un1_wadr_reg_12 & MEM_10_[0] ) | 
	(un1_wadr_reg_12 & din_reg[0] ) | 
	(MEM_10_[0] & din_reg[0] ));
  assign #(1)  un1_MEM_10_[1] = ((!un1_wadr_reg_12 & MEM_10_[1] ) | 
	(un1_wadr_reg_12 & din_reg[1] ) | 
	(MEM_10_[1] & din_reg[1] ));
  assign #(1)  un1_MEM_4_[0] = ((!un1_wadr_reg_6 & MEM_4_[0] ) | 
	(un1_wadr_reg_6 & din_reg[0] ) | 
	(MEM_4_[0] & din_reg[0] ));
  assign #(1)  un1_MEM_4_[1] = ((!un1_wadr_reg_6 & MEM_4_[1] ) | 
	(un1_wadr_reg_6 & din_reg[1] ) | 
	(MEM_4_[1] & din_reg[1] ));
  assign #(1)  un1_MEM_8_[0] = ((!un1_wadr_reg_10 & MEM_8_[0] ) | 
	(un1_wadr_reg_10 & din_reg[0] ) | 
	(MEM_8_[0] & din_reg[0] ));
  assign #(1)  un1_MEM_8_[1] = ((!un1_wadr_reg_10 & MEM_8_[1] ) | 
	(un1_wadr_reg_10 & din_reg[1] ) | 
	(MEM_8_[1] & din_reg[1] ));
  assign #(1)  un1_MEM_13_[0] = ((!un1_wadr_reg_16 & MEM_13_[0] ) | 
	(un1_wadr_reg_16 & din_reg[0] ) | 
	(MEM_13_[0] & din_reg[0] ));
  assign #(1)  un1_MEM_13_[1] = ((!un1_wadr_reg_16 & MEM_13_[1] ) | 
	(un1_wadr_reg_16 & din_reg[1] ) | 
	(MEM_13_[1] & din_reg[1] ));
  assign #(1)  un1_MEM_6_[0] = ((!un1_wadr_reg_8 & MEM_6_[0] ) | 
	(un1_wadr_reg_8 & din_reg[0] ) | 
	(MEM_6_[0] & din_reg[0] ));
  assign #(1)  un1_MEM_6_[1] = ((!un1_wadr_reg_8 & MEM_6_[1] ) | 
	(un1_wadr_reg_8 & din_reg[1] ) | 
	(MEM_6_[1] & din_reg[1] ));
  assign #(1)  un1_MEM_2_[0] = ((!un1_wadr_reg_3 & MEM_2_[0] ) | 
	(un1_wadr_reg_3 & din_reg[0] ) | 
	(MEM_2_[0] & din_reg[0] ));
  assign #(1)  un1_MEM_2_[1] = ((!un1_wadr_reg_3 & MEM_2_[1] ) | 
	(un1_wadr_reg_3 & din_reg[1] ) | 
	(MEM_2_[1] & din_reg[1] ));
  assign #(1)  un1_MEM_3_[0] = ((!un1_wadr_reg_4 & MEM_3_[0] ) | 
	(un1_wadr_reg_4 & din_reg[0] ) | 
	(MEM_3_[0] & din_reg[0] ));
  assign #(1)  un1_MEM_3_[1] = ((!un1_wadr_reg_4 & MEM_3_[1] ) | 
	(un1_wadr_reg_4 & din_reg[1] ) | 
	(MEM_3_[1] & din_reg[1] ));
  assign #(1)  un1_MEM_7_[0] = ((!un1_wadr_reg_5 & MEM_7_[0] ) | 
	(un1_wadr_reg_5 & din_reg[0] ) | 
	(MEM_7_[0] & din_reg[0] ));
  assign #(1)  un1_MEM_7_[1] = ((!un1_wadr_reg_5 & MEM_7_[1] ) | 
	(un1_wadr_reg_5 & din_reg[1] ) | 
	(MEM_7_[1] & din_reg[1] ));
  assign #(1)  un1_MEM_1_[0] = ((!un1_wadr_reg_7 & MEM_1_[0] ) | 
	(un1_wadr_reg_7 & din_reg[0] ) | 
	(MEM_1_[0] & din_reg[0] ));
  assign #(1)  un1_MEM_1_[1] = ((!un1_wadr_reg_7 & MEM_1_[1] ) | 
	(un1_wadr_reg_7 & din_reg[1] ) | 
	(MEM_1_[1] & din_reg[1] ));
  assign #(1)  RDOb[0] = 
	(un1_RAD0b_2 & MEM_0_[0] ) |
	(un1_RAD0b_3 & MEM_1_[0] ) |
	(un1_RAD1b_1 & MEM_2_[0] ) |
	(un1_RAD0b_4 & MEM_3_[0] ) |
	(un1_RAD2b_1 & MEM_4_[0] ) |
	(un1_RAD0b_5 & MEM_5_[0] ) |
	(un1_RAD1b_2 & MEM_6_[0] ) |
	(un1_RAD0b_6 & MEM_7_[0] ) |
	(un1_RAD3b_1 & MEM_8_[0] ) |
	(un1_RAD0b_7 & MEM_9_[0] ) |
	(un1_RAD1b_3 & MEM_10_[0] ) |
	(un1_RAD0b_8 & MEM_11_[0] ) |
	(un1_RAD2b_2 & MEM_12_[0] ) |
	(un1_RAD0b_9 & MEM_13_[0] ) |
	(un1_RAD1b_4 & MEM_14_[0] ) |
	(un1_RAD0b_1 & MEM_15_[0] );
  assign #(1)  RDOb[1] = 
	(un1_RAD0b_2 & MEM_0_[1] ) |
	(un1_RAD0b_3 & MEM_1_[1] ) |
	(un1_RAD1b_1 & MEM_2_[1] ) |
	(un1_RAD0b_4 & MEM_3_[1] ) |
	(un1_RAD2b_1 & MEM_4_[1] ) |
	(un1_RAD0b_5 & MEM_5_[1] ) |
	(un1_RAD1b_2 & MEM_6_[1] ) |
	(un1_RAD0b_6 & MEM_7_[1] ) |
	(un1_RAD3b_1 & MEM_8_[1] ) |
	(un1_RAD0b_7 & MEM_9_[1] ) |
	(un1_RAD1b_3 & MEM_10_[1] ) |
	(un1_RAD0b_8 & MEM_11_[1] ) |
	(un1_RAD2b_2 & MEM_12_[1] ) |
	(un1_RAD0b_9 & MEM_13_[1] ) |
	(un1_RAD1b_4 & MEM_14_[1] ) |
	(un1_RAD0b_1 & MEM_15_[1] );
  assign #(1)  WDOb[0] = 
	(un1_WAD0b_2 & MEM_0_[0] ) |
	(un1_WAD0b_3 & MEM_1_[0] ) |
	(un1_WAD1b_1 & MEM_2_[0] ) |
	(un1_WAD0b_4 & MEM_3_[0] ) |
	(un1_WAD2b_1 & MEM_4_[0] ) |
	(un1_WAD0b_5 & MEM_5_[0] ) |
	(un1_WAD1b_2 & MEM_6_[0] ) |
	(un1_WAD0b_6 & MEM_7_[0] ) |
	(un1_WAD3b_1 & MEM_8_[0] ) |
	(un1_WAD0b_7 & MEM_9_[0] ) |
	(un1_WAD1b_3 & MEM_10_[0] ) |
	(un1_WAD0b_8 & MEM_11_[0] ) |
	(un1_WAD2b_2 & MEM_12_[0] ) |
	(un1_WAD0b_9 & MEM_13_[0] ) |
	(un1_WAD1b_4 & MEM_14_[0] ) |
	(un1_WAD0b_1 & MEM_15_[0] );
  assign #(1)  WDOb[1] = 
	(un1_WAD0b_2 & MEM_0_[1] ) |
	(un1_WAD0b_3 & MEM_1_[1] ) |
	(un1_WAD1b_1 & MEM_2_[1] ) |
	(un1_WAD0b_4 & MEM_3_[1] ) |
	(un1_WAD2b_1 & MEM_4_[1] ) |
	(un1_WAD0b_5 & MEM_5_[1] ) |
	(un1_WAD1b_2 & MEM_6_[1] ) |
	(un1_WAD0b_6 & MEM_7_[1] ) |
	(un1_WAD3b_1 & MEM_8_[1] ) |
	(un1_WAD0b_7 & MEM_9_[1] ) |
	(un1_WAD1b_3 & MEM_10_[1] ) |
	(un1_WAD0b_8 & MEM_11_[1] ) |
	(un1_WAD2b_2 & MEM_12_[1] ) |
	(un1_WAD0b_9 & MEM_13_[1] ) |
	(un1_WAD1b_4 & MEM_14_[1] ) |
	(un1_WAD0b_1 & MEM_15_[1] );
  assign #(1)  WDO0 = WDOb[0];
  assign #(1)  WDO1 = WDOb[1];
  assign #(1)  RDO0 = RDOb[0];
  assign #(1)  RDO1 = RDOb[1];
  reg MEM_14__0_r_e_g; // dff
  always @(posedge un1_WCKb) MEM_14__0_r_e_g = #1 un1_MEM_14_[0];
    assign MEM_14_[0] = MEM_14__0_r_e_g;
  reg MEM_14__1_r_e_g; // dff
  always @(posedge un1_WCKb) MEM_14__1_r_e_g = #1 un1_MEM_14_[1];
    assign MEM_14_[1] = MEM_14__1_r_e_g;
  reg MEM_13__0_r_e_g; // dff
  always @(posedge un1_WCKb) MEM_13__0_r_e_g = #1 un1_MEM_13_[0];
    assign MEM_13_[0] = MEM_13__0_r_e_g;
  reg MEM_13__1_r_e_g; // dff
  always @(posedge un1_WCKb) MEM_13__1_r_e_g = #1 un1_MEM_13_[1];
    assign MEM_13_[1] = MEM_13__1_r_e_g;
  reg MEM_12__0_r_e_g; // dff
  always @(posedge un1_WCKb) MEM_12__0_r_e_g = #1 un1_MEM_12_[0];
    assign MEM_12_[0] = MEM_12__0_r_e_g;
  reg MEM_12__1_r_e_g; // dff
  always @(posedge un1_WCKb) MEM_12__1_r_e_g = #1 un1_MEM_12_[1];
    assign MEM_12_[1] = MEM_12__1_r_e_g;
  reg MEM_11__0_r_e_g; // dff
  always @(posedge un1_WCKb) MEM_11__0_r_e_g = #1 un1_MEM_11_[0];
    assign MEM_11_[0] = MEM_11__0_r_e_g;
  reg MEM_11__1_r_e_g; // dff
  always @(posedge un1_WCKb) MEM_11__1_r_e_g = #1 un1_MEM_11_[1];
    assign MEM_11_[1] = MEM_11__1_r_e_g;
  reg MEM_10__0_r_e_g; // dff
  always @(posedge un1_WCKb) MEM_10__0_r_e_g = #1 un1_MEM_10_[0];
    assign MEM_10_[0] = MEM_10__0_r_e_g;
  reg MEM_10__1_r_e_g; // dff
  always @(posedge un1_WCKb) MEM_10__1_r_e_g = #1 un1_MEM_10_[1];
    assign MEM_10_[1] = MEM_10__1_r_e_g;
  reg MEM_9__0_r_e_g; // dff
  always @(posedge un1_WCKb) MEM_9__0_r_e_g = #1 un1_MEM_9_[0];
    assign MEM_9_[0] = MEM_9__0_r_e_g;
  reg MEM_9__1_r_e_g; // dff
  always @(posedge un1_WCKb) MEM_9__1_r_e_g = #1 un1_MEM_9_[1];
    assign MEM_9_[1] = MEM_9__1_r_e_g;
  reg MEM_8__0_r_e_g; // dff
  always @(posedge un1_WCKb) MEM_8__0_r_e_g = #1 un1_MEM_8_[0];
    assign MEM_8_[0] = MEM_8__0_r_e_g;
  reg MEM_8__1_r_e_g; // dff
  always @(posedge un1_WCKb) MEM_8__1_r_e_g = #1 un1_MEM_8_[1];
    assign MEM_8_[1] = MEM_8__1_r_e_g;
  reg MEM_7__0_r_e_g; // dff
  always @(posedge un1_WCKb) MEM_7__0_r_e_g = #1 un1_MEM_7_[0];
    assign MEM_7_[0] = MEM_7__0_r_e_g;
  reg MEM_7__1_r_e_g; // dff
  always @(posedge un1_WCKb) MEM_7__1_r_e_g = #1 un1_MEM_7_[1];
    assign MEM_7_[1] = MEM_7__1_r_e_g;
  reg MEM_6__0_r_e_g; // dff
  always @(posedge un1_WCKb) MEM_6__0_r_e_g = #1 un1_MEM_6_[0];
    assign MEM_6_[0] = MEM_6__0_r_e_g;
  reg MEM_6__1_r_e_g; // dff
  always @(posedge un1_WCKb) MEM_6__1_r_e_g = #1 un1_MEM_6_[1];
    assign MEM_6_[1] = MEM_6__1_r_e_g;
  reg MEM_5__0_r_e_g; // dff
  always @(posedge un1_WCKb) MEM_5__0_r_e_g = #1 un1_MEM_5_[0];
    assign MEM_5_[0] = MEM_5__0_r_e_g;
  reg MEM_5__1_r_e_g; // dff
  always @(posedge un1_WCKb) MEM_5__1_r_e_g = #1 un1_MEM_5_[1];
    assign MEM_5_[1] = MEM_5__1_r_e_g;
  reg MEM_4__0_r_e_g; // dff
  always @(posedge un1_WCKb) MEM_4__0_r_e_g = #1 un1_MEM_4_[0];
    assign MEM_4_[0] = MEM_4__0_r_e_g;
  reg MEM_4__1_r_e_g; // dff
  always @(posedge un1_WCKb) MEM_4__1_r_e_g = #1 un1_MEM_4_[1];
    assign MEM_4_[1] = MEM_4__1_r_e_g;
  reg MEM_3__0_r_e_g; // dff
  always @(posedge un1_WCKb) MEM_3__0_r_e_g = #1 un1_MEM_3_[0];
    assign MEM_3_[0] = MEM_3__0_r_e_g;
  reg MEM_3__1_r_e_g; // dff
  always @(posedge un1_WCKb) MEM_3__1_r_e_g = #1 un1_MEM_3_[1];
    assign MEM_3_[1] = MEM_3__1_r_e_g;
  reg MEM_2__0_r_e_g; // dff
  always @(posedge un1_WCKb) MEM_2__0_r_e_g = #1 un1_MEM_2_[0];
    assign MEM_2_[0] = MEM_2__0_r_e_g;
  reg MEM_2__1_r_e_g; // dff
  always @(posedge un1_WCKb) MEM_2__1_r_e_g = #1 un1_MEM_2_[1];
    assign MEM_2_[1] = MEM_2__1_r_e_g;
  reg MEM_1__0_r_e_g; // dff
  always @(posedge un1_WCKb) MEM_1__0_r_e_g = #1 un1_MEM_1_[0];
    assign MEM_1_[0] = MEM_1__0_r_e_g;
  reg MEM_1__1_r_e_g; // dff
  always @(posedge un1_WCKb) MEM_1__1_r_e_g = #1 un1_MEM_1_[1];
    assign MEM_1_[1] = MEM_1__1_r_e_g;
  reg MEM_0__0_r_e_g; // dff
  always @(posedge un1_WCKb) MEM_0__0_r_e_g = #1 un1_MEM_0_[0];
    assign MEM_0_[0] = MEM_0__0_r_e_g;
  reg MEM_0__1_r_e_g; // dff
  always @(posedge un1_WCKb) MEM_0__1_r_e_g = #1 un1_MEM_0_[1];
    assign MEM_0_[1] = MEM_0__1_r_e_g;
  reg MEM_15__0_r_e_g; // dff
  always @(posedge un1_WCKb) MEM_15__0_r_e_g = #1 un1_MEM_15_[0];
    assign MEM_15_[0] = MEM_15__0_r_e_g;
  reg MEM_15__1_r_e_g; // dff
  always @(posedge un1_WCKb) MEM_15__1_r_e_g = #1 un1_MEM_15_[1];
    assign MEM_15_[1] = MEM_15__1_r_e_g;
  reg din_reg_0_r_e_g; // dff
  always @(posedge WCKb) din_reg_0_r_e_g = #1 din_reg_4[0];
    assign din_reg[0] = din_reg_0_r_e_g;
  reg din_reg_1_r_e_g; // dff
  always @(posedge WCKb) din_reg_1_r_e_g = #1 din_reg_4[1];
    assign din_reg[1] = din_reg_1_r_e_g;
  reg wadr_reg_0_r_e_g; // dffr
  always @(posedge WCKb or posedge un1_GSR ) wadr_reg_0_r_e_g = #1 un1_GSR ? 1'b0 : WAD0b ;
    assign wadr_reg[0] = wadr_reg_0_r_e_g;
  reg wadr_reg_1_r_e_g; // dffr
  always @(posedge WCKb or posedge un1_GSR ) wadr_reg_1_r_e_g = #1 un1_GSR ? 1'b0 : WAD1b ;
    assign wadr_reg[1] = wadr_reg_1_r_e_g;
  reg wadr_reg_2_r_e_g; // dffr
  always @(posedge WCKb or posedge un1_GSR ) wadr_reg_2_r_e_g = #1 un1_GSR ? 1'b0 : WAD2b ;
    assign wadr_reg[2] = wadr_reg_2_r_e_g;
  reg wadr_reg_3_r_e_g; // dffr
  always @(posedge WCKb or posedge un1_GSR ) wadr_reg_3_r_e_g = #1 un1_GSR ? 1'b0 : WAD3b ;
    assign wadr_reg[3] = wadr_reg_3_r_e_g;
//@2:1
  assign GND = 1'b0;
//@2:1
  assign VCC = 1'b1;
endmodule /* DPR16X2B */

module AND2 (
  A,
  B,
  Z
);
input A ;
input B ;
output Z ;
wire A ;
wire B ;
wire Z ;
wire GND ;
wire VCC ;
  assign #(1)  Z = (B  & A );
//@2:1
  assign GND = 1'b0;
//@2:1
  assign VCC = 1'b1;
endmodule /* AND2 */

module dpram16x8_8 (
  tsr_tmp,
  data_in,
  top_i,
  bottom,
  we_en1_c,
  VCC,
  rst_c,
  un1_EF_1,
  GND,
  clk_c,
  un1_top_axbxc3,
  un1_top_axbxc2,
  un1_top_axbxc1
);
output [7:0] tsr_tmp ;
input [7:0] data_in ;
input [0:0] top_i ;
input [3:0] bottom ;
input we_en1_c ;
input VCC ;
input rst_c ;
input un1_EF_1 ;
input GND ;
input clk_c ;
input un1_top_axbxc3 ;
input un1_top_axbxc2 ;
input un1_top_axbxc1 ;
wire we_en1_c ;
wire VCC ;
wire rst_c ;
wire un1_EF_1 ;
wire GND ;
wire clk_c ;
wire un1_top_axbxc3 ;
wire un1_top_axbxc2 ;
wire un1_top_axbxc1 ;
wire WDO0 ;
wire WDO1 ;
wire WDO0_0 ;
wire WDO1_0 ;
wire WDO0_1 ;
wire WDO1_1 ;
wire WDO0_2 ;
wire WDO1_2 ;
wire dataout0_ffin ;
wire FF_0_QN ;
wire dataout1_ffin ;
wire FF_1_QN ;
wire dataout2_ffin ;
wire FF_2_QN ;
wire dataout3_ffin ;
wire FF_3_QN ;
wire dataout4_ffin ;
wire FF_4_QN ;
wire dataout5_ffin ;
wire FF_5_QN ;
wire dataout6_ffin ;
wire FF_6_QN ;
wire dataout7_ffin ;
wire FF_7_QN ;
wire dec_wre3 ;
wire NN_1 ;
wire NN_2 ;
// @9:24
  DPR16X2B mem_0_3_Z (
	.RDO0(dataout0_ffin),
	.RDO1(dataout1_ffin),
	.WDO0(WDO0),
	.WDO1(WDO1),
	.RAD0(bottom[0]),
	.RAD1(bottom[1]),
	.RAD2(bottom[2]),
	.RAD3(bottom[3]),
	.WAD0(top_i[0]),
	.WAD1(un1_top_axbxc1),
	.WAD2(un1_top_axbxc2),
	.WAD3(un1_top_axbxc3),
	.DI0(data_in[0]),
	.DI1(data_in[1]),
	.WRE(dec_wre3),
	.WCK(clk_c),
	.GSR(GND)
);
// @9:24
  DPR16X2B mem_0_2_Z (
	.RDO0(dataout2_ffin),
	.RDO1(dataout3_ffin),
	.WDO0(WDO0_0),
	.WDO1(WDO1_0),
	.RAD0(bottom[0]),
	.RAD1(bottom[1]),
	.RAD2(bottom[2]),
	.RAD3(bottom[3]),
	.WAD0(top_i[0]),
	.WAD1(un1_top_axbxc1),
	.WAD2(un1_top_axbxc2),
	.WAD3(un1_top_axbxc3),
	.DI0(data_in[2]),
	.DI1(data_in[3]),
	.WRE(dec_wre3),
	.WCK(clk_c),
	.GSR(GND)
);
// @9:24
  DPR16X2B mem_0_1_Z (
	.RDO0(dataout4_ffin),
	.RDO1(dataout5_ffin),
	.WDO0(WDO0_1),
	.WDO1(WDO1_1),
	.RAD0(bottom[0]),
	.RAD1(bottom[1]),
	.RAD2(bottom[2]),
	.RAD3(bottom[3]),
	.WAD0(top_i[0]),
	.WAD1(un1_top_axbxc1),
	.WAD2(un1_top_axbxc2),
	.WAD3(un1_top_axbxc3),
	.DI0(data_in[4]),
	.DI1(data_in[5]),
	.WRE(dec_wre3),
	.WCK(clk_c),
	.GSR(GND)
);
// @9:24
  DPR16X2B mem_0_0_Z (
	.RDO0(dataout6_ffin),
	.RDO1(dataout7_ffin),
	.WDO0(WDO0_2),
	.WDO1(WDO1_2),
	.RAD0(bottom[0]),
	.RAD1(bottom[1]),
	.RAD2(bottom[2]),
	.RAD3(bottom[3]),
	.WAD0(top_i[0]),
	.WAD1(un1_top_axbxc1),
	.WAD2(un1_top_axbxc2),
	.WAD3(un1_top_axbxc3),
	.DI0(data_in[6]),
	.DI1(data_in[7]),
	.WRE(dec_wre3),
	.WCK(clk_c),
	.GSR(GND)
);
// @9:24
  FD1P3DX FF_0_Z (
	.D(dataout0_ffin),
	.SP(un1_EF_1),
	.CK(clk_c),
	.CD(rst_c),
	.Q(tsr_tmp[0]),
	.QN(FF_0_QN),
	.GSR(VCC)
);
// @9:24
  FD1P3DX FF_1_Z (
	.D(dataout1_ffin),
	.SP(un1_EF_1),
	.CK(clk_c),
	.CD(rst_c),
	.Q(tsr_tmp[1]),
	.QN(FF_1_QN),
	.GSR(VCC)
);
// @9:24
  FD1P3DX FF_2_Z (
	.D(dataout2_ffin),
	.SP(un1_EF_1),
	.CK(clk_c),
	.CD(rst_c),
	.Q(tsr_tmp[2]),
	.QN(FF_2_QN),
	.GSR(VCC)
);
// @9:24
  FD1P3DX FF_3_Z (
	.D(dataout3_ffin),
	.SP(un1_EF_1),
	.CK(clk_c),
	.CD(rst_c),
	.Q(tsr_tmp[3]),
	.QN(FF_3_QN),
	.GSR(VCC)
);
// @9:24
  FD1P3DX FF_4_Z (
	.D(dataout4_ffin),
	.SP(un1_EF_1),
	.CK(clk_c),
	.CD(rst_c),
	.Q(tsr_tmp[4]),
	.QN(FF_4_QN),
	.GSR(VCC)
);
// @9:24
  FD1P3DX FF_5_Z (
	.D(dataout5_ffin),
	.SP(un1_EF_1),
	.CK(clk_c),
	.CD(rst_c),
	.Q(tsr_tmp[5]),
	.QN(FF_5_QN),
	.GSR(VCC)
);
// @9:24
  FD1P3DX FF_6_Z (
	.D(dataout6_ffin),
	.SP(un1_EF_1),
	.CK(clk_c),
	.CD(rst_c),
	.Q(tsr_tmp[6]),
	.QN(FF_6_QN),
	.GSR(VCC)
);
// @9:24