uart4.vm

一个UART的FPGA core

//
// Written by Synplify
// Synplify 8.4.0.p, Build 020R.
// Fri Jul 07 14:16:33 2006
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "noname"
// file 1 "noname"
// file 2 "\d:\isptools5_1\synpbase\lib\lucent\machxo.v "
// file 3 "\d:\isptools5_1\ispcpld\generic\verilog\synplify\generic.v "
// file 4 "\d:\isptools5_1\ispcpld\..\cae_library\synthesis\verilog\machxo.v "
// file 5 "\e:\yiluo\dd\uart.h "
// file 6 "\e:\yiluo\dd\data_path.v "
// file 7 "\e:\yiluo\dd\inter.v "
// file 8 "\e:\yiluo\dd\dpram16x8.v "
// file 9 "\e:\yiluo\dd\uart_fifo.v "
// file 10 "\e:\yiluo\dd\rcvr.v "
// file 11 "\e:\yiluo\dd\txmit.v "
// file 12 "\e:\yiluo\dd\baud1.v "
// file 13 "\e:\yiluo\dd\decode.v "
// file 14 "\e:\yiluo\dd\uart4_top.v "

`timescale 100 ps/100 ps
module VLO (
  Z
);
output Z ;
wire Z ;
wire GND ;
wire VCC ;
  assign GND = 1'b0;
//@2:1
  assign VCC = 1'b1;
assign Z = GND;
endmodule /* VLO */

module VHI (
  Z
);
output Z ;
wire Z ;
wire VCC ;
wire GND ;
  assign VCC = 1'b1;
//@2:1
  assign GND = 1'b0;
assign Z = VCC;
endmodule /* VHI */

module INV (
  A,
  Z
);
input A ;
output Z ;
wire A ;
wire Z ;
wire GND ;
wire VCC ;
  assign #(1)  Z = ~ A;
//@2:1
  assign GND = 1'b0;
//@2:1
  assign VCC = 1'b1;
endmodule /* INV */

module OB (
  I,
  O
);
input I ;
output O ;
wire I ;
wire O ;
wire GND ;
wire VCC ;
  assign #(1)  O = I;
//@2:1
  assign GND = 1'b0;
//@2:1
  assign VCC = 1'b1;
endmodule /* OB */

module IB (
  I,
  O
);
input I ;
output O ;
wire I ;
wire O ;
wire GND ;
wire VCC ;
  assign #(1)  O = I;
//@2:1
  assign GND = 1'b0;
//@2:1
  assign VCC = 1'b1;
endmodule /* IB */

module BB (
  B,
  I,
  T,
  O
);
inout B /* synthesis syn_tristate = 1 */;
input I ;
input T ;
output O ;
wire B ;
wire I ;
wire T ;
wire O ;
wire ti ;
wire GND ;
wire VCC ;
  assign #(1)  ti = ~ T;
  assign #(1)  B = ti ? I : 1'bz;
  assign #(1)  O = B;
//@2:1
  assign GND = 1'b0;
//@2:1
  assign VCC = 1'b1;
endmodule /* BB */

module FD1P3AX (
  D,
  SP,
  CK,
  Q,
  QN,
  GSR
);
input D ;
input SP ;
input CK ;
output Q ;
output QN ;
input GSR ;
wire D ;
wire SP ;
wire CK ;
wire Q ;
wire QN ;
wire GSR ;
wire gsrn ;
wire m ;
wire GND ;
wire VCC ;
  assign #(1)  gsrn = ~ GSR;
  assign #(1)  m = ((!SP & Q ) | 
	(SP & D ) | 
	(Q & D ));
  reg Q_r_e_g; // dffr
  always @(posedge CK or posedge gsrn ) Q_r_e_g = #1 gsrn ? 1'b0 : m ;
    assign Q = Q_r_e_g;
  initial Q_r_e_g = 0; // initial value for register/latch
  assign #(1)  QN = ~ Q;
//@2:1
  assign GND = 1'b0;
//@2:1
  assign VCC = 1'b1;
endmodule /* FD1P3AX */

module decode_1 (
  addr_c,
  A_0,
  A_4,
  A_1,
  oe_n_c,
  inter_pos2,
  inter_pos0,
  fifor3_cs,
  fifor2_cs,
  N_71,
  fifor0_cs,
  N_76,
  fifot3_cs,
  fifot2_cs,
  N_65,
  inter_mask,
  GND,
  cs_n_c,
  VCC,
  clk_c,
  N_72,
  we_n_c,
  N_63
);
input [4:0] addr_c ;
output A_0 ;
output A_4 ;
output A_1 ;
input oe_n_c ;
output inter_pos2 ;
output inter_pos0 ;
output fifor3_cs ;
output fifor2_cs ;
output N_71 ;
output fifor0_cs ;
output N_76 ;
output fifot3_cs ;
output fifot2_cs ;
output N_65 ;
output inter_mask ;
input GND ;
input cs_n_c ;
input VCC ;
input clk_c ;
output N_72 ;
input we_n_c ;
output N_63 ;
wire A_0 ;
wire A_4 ;
wire A_1 ;
wire oe_n_c ;
wire inter_pos2 ;
wire inter_pos0 ;
wire fifor3_cs ;
wire fifor2_cs ;
wire N_71 ;
wire fifor0_cs ;
wire N_76 ;
wire fifot3_cs ;
wire fifot2_cs ;
wire N_65 ;
wire inter_mask ;
wire GND ;
wire cs_n_c ;
wire VCC ;
wire clk_c ;
wire N_72 ;
wire we_n_c ;
wire N_63 ;
wire [3:2] A;
wire Q_QN_249 ;
wire Q_QN_250 ;
wire Q_QN_251 ;
wire Q_QN_252 ;
wire Q_QN_253 ;
wire N_68 ;
wire N_24_i ;
wire inter_mask_0_a3_1 ;
wire N_67 ;
wire NN_1 ;
wire NN_2 ;
assign N_72 = (N_63 & ~A_1 & ~we_n_c & ~A[2]);
// @13:22
  FD1P3AX \A_4_.Q_Z  (
	.D(addr_c[4]),
	.SP(N_24_i),
	.CK(clk_c),
	.Q(A_4),
	.QN(Q_QN_249),
	.GSR(VCC)
);
// @13:22
  FD1P3AX \A_3_.Q_Z  (
	.D(addr_c[3]),
	.SP(N_24_i),
	.CK(clk_c),
	.Q(A[3]),
	.QN(Q_QN_250),
	.GSR(VCC)
);
// @13:22
  FD1P3AX \A_2_.Q_Z  (
	.D(addr_c[2]),
	.SP(N_24_i),
	.CK(clk_c),
	.Q(A[2]),
	.QN(Q_QN_251),
	.GSR(VCC)
);
// @13:22
  FD1P3AX \A_1_.Q_Z  (
	.D(addr_c[1]),
	.SP(N_24_i),
	.CK(clk_c),
	.Q(A_1),
	.QN(Q_QN_252),
	.GSR(VCC)
);
// @13:22
  FD1P3AX \A_0_.Q_Z  (
	.D(addr_c[0]),
	.SP(N_24_i),
	.CK(clk_c),
	.Q(A_0),
	.QN(Q_QN_253),
	.GSR(VCC)
);
assign N_68 = (A_1 & ~A[3] & ~cs_n_c);
assign inter_mask = (~A_1 & A[2] & N_67 & inter_mask_0_a3_1);
assign fifot2_cs = (~A_0 & A_4 & N_65 & N_68);
assign fifot3_cs = (A_0 & A_4 & N_65 & N_68);
assign fifor0_cs = (~A_0 & A_4 & N_76);
assign fifor2_cs = (~A_0 & A_4 & N_71);
assign fifor3_cs = (A_0 & A_4 & N_71);
assign inter_pos0 = (N_67 & N_76);
assign inter_pos2 = (N_67 & N_71);
assign N_71 = (~oe_n_c & A[2] & N_68);
assign N_76 = (~oe_n_c & ~A_1 & A[2] & N_63);
assign N_24_i = (~cs_n_c & ~oe_n_c) | (~cs_n_c & ~we_n_c) | (~cs_n_c & 
   ~oe_n_c & we_n_c);
assign inter_mask_0_a3_1 = (~cs_n_c & A[3] & ~we_n_c);
assign N_63 = (~cs_n_c & ~A[3]);
assign N_65 = (~A[2] & ~we_n_c);
assign N_67 = (~A_0 & ~A_4);
//@2:1
  assign NN_1 = 1'b0;
//@2:1
  assign NN_2 = 1'b1;
endmodule /* decode_1 */

module FD1S3BX (
  D,
  CK,
  PD,
  Q,
  QN,
  GSR
);
input D ;
input CK ;
input PD ;
output Q ;
output QN ;
input GSR ;
wire D ;
wire CK ;
wire PD ;
wire Q ;
wire QN ;
wire GSR ;
wire gsrn ;
wire pre ;
wire GND ;
wire VCC ;
  assign #(1)  gsrn = ~ GSR;
  assign #(1)  pre = (PD  | gsrn );
  reg Q_r_e_g; // dffs
  always @(posedge CK or posedge pre ) Q_r_e_g = #1 pre ? 1'b1 : D;
    assign Q = Q_r_e_g;
  initial Q_r_e_g = 1; // initial value for register/latch
  assign #(1)  QN = ~ Q;
//@2:1
  assign GND = 1'b0;
//@2:1
  assign VCC = 1'b1;
endmodule /* FD1S3BX */

module FD1S3DX (
  D,
  CK,
  CD,
  Q,
  QN,
  GSR
);
input D ;
input CK ;
input CD ;
output Q ;
output QN ;
input GSR ;
wire D ;
wire CK ;
wire CD ;
wire Q ;
wire QN ;
wire GSR ;
wire gsrn ;
wire clr ;
wire GND ;
wire VCC ;
  assign #(1)  gsrn = ~ GSR;
  assign #(1)  clr = (CD  | gsrn );
  reg Q_r_e_g; // dffr
  always @(posedge CK or posedge clr ) Q_r_e_g = #1 clr ? 1'b0 : D ;
    assign Q = Q_r_e_g;
  initial Q_r_e_g = 0; // initial value for register/latch
  assign #(1)  QN = ~ Q;
//@2:1
  assign GND = 1'b0;
//@2:1
  assign VCC = 1'b1;
endmodule /* FD1S3DX */

module baud_1 (
  baud_clk_c,
  baud_clk1_c,
  GND,
  VCC,
  rst_c,
  clk_in_c
);
output baud_clk_c ;
output baud_clk1_c ;
input GND ;
input VCC ;
input rst_c ;
input clk_in_c ;
wire baud_clk_c ;
wire baud_clk1_c ;
wire GND ;
wire VCC ;
wire rst_c ;
wire clk_in_c ;
wire [0:0] sys_clk_cnt_i;
wire [8:7] sys_clk_cnt_5;
wire [8:0] sys_clk_cnt;
wire Q_QN_231 ;
wire Q_QN_232 ;
wire Q_QN_233 ;
wire Q_QN_234 ;
wire Q_QN_235 ;
wire Q_QN_236 ;
wire Q_QN_237 ;
wire Q_QN_238 ;
wire Q_QN_239 ;
wire un6_sys_clk_cnt_s_8_0_COUT0 ;
wire NC0 ;
wire NC1 ;
wire un6_sys_clk_cnt_cry_6_0_COUT0 ;
wire un6_sys_clk_cnt_cry_6_0_COUT1 ;
wire un6_sys_clk_cnt_cry_6_0_S0 ;
wire un6_sys_clk_cnt_cry_4_0_COUT0 ;
wire un6_sys_clk_cnt_cry_4_0_COUT1 ;
wire un6_sys_clk_cnt_cry_4_0_S0 ;
wire un6_sys_clk_cnt_cry_4_0_S1 ;
wire un6_sys_clk_cnt_cry_2_0_COUT0 ;
wire un6_sys_clk_cnt_cry_2_0_COUT1 ;
wire un6_sys_clk_cnt_cry_2_0_S0 ;
wire un6_sys_clk_cnt_cry_2_0_S1 ;
wire un6_sys_clk_cnt_cry_0_0_COUT0 ;
wire un6_sys_clk_cnt_cry_0_0_COUT1 ;
wire un6_sys_clk_cnt_cry_0_0_S0 ;
wire un6_sys_clk_cnt_cry_0_0_S1 ;
wire un6_sys_clk_cnt_s_8_0_S0 ;
wire un6_sys_clk_cnt_cry_6_0_S1 ;
wire un2_baud_clk1lto6 ;
wire sys_clk_cnt17_4 ;
wire sys_clk_cnt17_3 ;
wire un2_baud_clk1lto4_1 ;
wire un4_baud_clk1lto7_0 ;
wire un6_sys_clk_cnt_axb_8 ;
wire un6_sys_clk_cnt_axb_7 ;
wire un6_sys_clk_cnt_axb_6 ;
wire un6_sys_clk_cnt_axb_5 ;
wire un6_sys_clk_cnt_axb_4 ;
wire un6_sys_clk_cnt_axb_3 ;
wire un6_sys_clk_cnt_axb_2 ;
wire un6_sys_clk_cnt_axb_1 ;
wire un6_sys_clk_cnt_axb_0 ;
wire un2_baud_clk1lto6_1 ;
wire NN_1 ;
wire NN_2 ;
// @14:40
  INV \sys_clk_cnt_i_cZ[0]  (
	.A(sys_clk_cnt[0]),
	.Z(sys_clk_cnt_i[0])
);
// @12:11
  FD1S3BX \sys_clk_cnt_8_.Q_Z  (
	.D(sys_clk_cnt_5[8]),
	.CK(clk_in_c),
	.PD(rst_c),
	.Q(sys_clk_cnt[8]),
	.QN(Q_QN_231),
	.GSR(VCC)
);
// @12:11
  FD1S3DX \sys_clk_cnt_7_.Q_Z  (
	.D(sys_clk_cnt_5[7]),
	.CK(clk_in_c),
	.CD(rst_c),
	.Q(sys_clk_cnt[7]),
	.QN(Q_QN_232),
	.GSR(VCC)
);
// @12:11
  FD1S3DX \sys_clk_cnt_6_.Q_Z  (
	.D(un6_sys_clk_cnt_cry_6_0_S0),
	.CK(clk_in_c),
	.CD(rst_c),
	.Q(sys_clk_cnt[6]),
	.QN(Q_QN_233),
	.GSR(VCC)
);
// @12:11
  FD1S3DX \sys_clk_cnt_5_.Q_Z  (
	.D(un6_sys_clk_cnt_cry_4_0_S1),
	.CK(clk_in_c),
	.CD(rst_c),
	.Q(sys_clk_cnt[5]),
	.QN(Q_QN_234),
	.GSR(VCC)
);
// @12:11
  FD1S3DX \sys_clk_cnt_4_.Q_Z  (
	.D(un6_sys_clk_cnt_cry_4_0_S0),
	.CK(clk_in_c),
	.CD(rst_c),
	.Q(sys_clk_cnt[4]),
	.QN(Q_QN_235),
	.GSR(VCC)
);
// @12:11
  FD1S3DX \sys_clk_cnt_3_.Q_Z  (
	.D(un6_sys_clk_cnt_cry_2_0_S1),
	.CK(clk_in_c),
	.CD(rst_c),
	.Q(sys_clk_cnt[3]),
	.QN(Q_QN_236),
	.GSR(VCC)
);
// @12:11
  FD1S3DX \sys_clk_cnt_2_.Q_Z  (
	.D(un6_sys_clk_cnt_cry_2_0_S0),
	.CK(clk_in_c),
	.CD(rst_c),
	.Q(sys_clk_cnt[2]),
	.QN(Q_QN_237),
	.GSR(VCC)
);
// @12:11
  FD1S3DX \sys_clk_cnt_1_.Q_Z  (
	.D(un6_sys_clk_cnt_cry_0_0_S1),
	.CK(clk_in_c),
	.CD(rst_c),
	.Q(sys_clk_cnt[1]),
	.QN(Q_QN_238),
	.GSR(VCC)
);
// @12:11
  FD1S3DX \sys_clk_cnt_0_.Q_Z  (
	.D(sys_clk_cnt_i[0]),
	.CK(clk_in_c),
	.CD(rst_c),