baud.v

一个UART的FPGA core

`timescale 1ns/100ps
module baud(clk,rst,
            baud_cs0,baud_cs1,baud_cs2,baud_cs3,
	        data,
			baud_clk0,baud_clk1,baud_clk2,baud_clk3
		    );

input clk,rst;
input baud_cs0,baud_cs1,baud_cs2,baud_cs3;
input [7:0] data;
output baud_clk0,baud_clk1 ,baud_clk2,baud_clk3;

reg baud_clk0,baud_clk1 ,baud_clk2,baud_clk3;
reg [1:0] baud_reg0,baud_reg1, baud_reg2,baud_reg3;//baud rate register
reg [3:0] baud_cnt;//调整它就可以根据不同输入频率选baudrate

////////////////////////////baud select referance //////
always @(negedge clk) if(baud_cs0) baud_reg0 <= data[1:0];
always @(negedge clk) if(baud_cs1) baud_reg1 <= data[1:0];
always @(negedge clk) if(baud_cs2) baud_reg2 <= data[1:0];
always @(negedge clk) if(baud_cs3) baud_reg3 <= data[1:0];

///////////////////////////////baud_cnt  generator////////////////////

always @ ( posedge clk or posedge rst )
if (rst )	baud_cnt <= 0;
else    	baud_cnt <= baud_cnt + 1;

///////////////////////////////baud_select  ////////////////////

    always @ ( posedge clk )
		casex ( baud_reg0 )
			2'b00:	baud_clk0 <= baud_cnt [3];
			2'b01:	baud_clk0 <= baud_cnt [2];
			2'b10:	baud_clk0 <= baud_cnt [1];
			2'b11:	baud_clk0 <= baud_cnt [0];
			default:	baud_clk0 <= baud_cnt [3];
		endcase

	always @ (  posedge clk )
		casex ( baud_reg1 )
			2'b00:	baud_clk1 <= baud_cnt [3];
			2'b01:	baud_clk1 <= baud_cnt [2];
			2'b10:	baud_clk1 <= baud_cnt [1];
			2'b11:	baud_clk1 <= baud_cnt [0];
			default:	baud_clk1 <= baud_cnt [3];
		endcase


	always @ ( posedge clk)
		casex ( baud_reg2 )
			2'b00:	baud_clk2 <= baud_cnt [3];
			2'b01:	baud_clk2 <= baud_cnt [2];
			2'b10:	baud_clk2 <= baud_cnt [1];
			2'b11:	baud_clk2 <= baud_cnt [0];
			default:	baud_clk2 <= baud_cnt [3];
		endcase


	always @ (  posedge clk )
		casex ( baud_reg3 )
			2'b00:	baud_clk3 <= baud_cnt [3];
			2'b01:	baud_clk3 <= baud_cnt [2];
			2'b10:	baud_clk3 <= baud_cnt [1];
			2'b11:  baud_clk3 <= baud_cnt [0];
			default:	baud_clk3 <= baud_cnt [3];
		endcase

endmodule