uart4.tlg

一个UART的FPGA core

Selecting top level module Uart4
@N: CG364 :"E:\yiluo\dd\decode.v":2:7:2:12|Synthesizing module decode

@W: CL159 :"E:\yiluo\dd\decode.v":12:13:12:16|Input data is unused
@N: CG364 :"E:\yiluo\dd\baud1.v":1:7:1:10|Synthesizing module baud

@N: CG364 :"d:\ispTOOLS5_1\ispcpld\..\cae_library\synthesis\verilog\machxo.v":185:7:185:10|Synthesizing module AND2

@N: CG364 :"d:\ispTOOLS5_1\ispcpld\..\cae_library\synthesis\verilog\machxo.v":337:7:337:13|Synthesizing module FD1P3DX

@N: CG364 :"d:\ispTOOLS5_1\ispcpld\..\cae_library\synthesis\verilog\machxo.v":107:7:107:14|Synthesizing module DPR16X2B

@N: CG364 :"E:\yiluo\dd\dpram16x8.v":8:7:8:15|Synthesizing module dpram16x8

@N: CG364 :"E:\yiluo\dd\uart_fifo.v":3:7:3:15|Synthesizing module UART_FIFO

@N: CG364 :"E:\yiluo\dd\txmit.v":3:7:3:11|Synthesizing module txmit

@W: CL159 :"E:\yiluo\dd\txmit.v":10:16:10:21|Input clk_in is unused
@N: CG364 :"E:\yiluo\dd\rcvr.v":3:7:3:10|Synthesizing module rcvr

@W: CL169 :"E:\yiluo\dd\rcvr.v":51:0:51:5|Pruning Register state1_4 

@N: CG364 :"E:\yiluo\dd\inter.v":2:8:2:12|Synthesizing module inter

@W: CL159 :"E:\yiluo\dd\inter.v":7:10:7:12|Input csn is unused
@W: CL159 :"E:\yiluo\dd\inter.v":7:14:7:15|Input we is unused
@W: CL159 :"E:\yiluo\dd\inter.v":8:12:8:15|Input addr is unused
@N: CG364 :"E:\yiluo\dd\data_path.v":2:7:2:15|Synthesizing module data_path

@N: CG364 :"E:\yiluo\dd\uart4_top.v":3:7:3:11|Synthesizing module Uart4

@W: CL156 :"E:\yiluo\dd\uart4_top.v":71:8:71:10|*Input csn to this expression [instance] has undriven bits which are being tied to 0 - a simulation mismatch is possible
@W: CL156 :"E:\yiluo\dd\uart4_top.v":71:8:71:10|*Input we to this expression [instance] has undriven bits which are being tied to 0 - a simulation mismatch is possible