decode.v.bak

一个UART的FPGA core

`timescale 1ns/100ps
module decode( clk,addr,data,cs_n,we_n,oe_n,//input
               baud_cs0,baud_cs1,baud_cs2,baud_cs3,
               fifot0_cs,fifot1_cs,fifot2_cs,fifot3_cs,
			   fifor0_cs,fifor1_cs,fifor2_cs,fifor3_cs,
			   inter_pos0,inter_pos1,inter_pos2,inter_pos3,inter_pos4,inter_pos5,inter_pos6,inter_pos7,
               inter_mask
              );
input  clk;
input  [4:0] addr;
input  cs_n,we_n,oe_n;
input  [7:0] data;
output baud_cs0,baud_cs1,baud_cs2,baud_cs3;
output inter_pos0,inter_pos1,inter_pos2,inter_pos3,inter_pos4,inter_pos5,inter_pos6,inter_pos7;
output fifot0_cs,fifot1_cs,fifot2_cs,fifot3_cs;
output fifor0_cs,fifor1_cs,fifor2_cs,fifor3_cs;
output inter_mask;

reg [4:0] A ;
//reg [4:0] B ;

always @(posedge clk)  if((!we_n | !oe_n )& !cs_n)  A <= addr;
//always @(negedge oe_n)  if(!we_n & !cs_n)  B <= addr;

assign baud_cs0 = ~A[4] & ~A[3] & ~A[2] & ~A[1] & ~A[0] & ~cs_n & ~we_n;  //0x0
assign baud_cs1 = ~A[4] & ~A[3] & ~A[2] & ~A[1] & A[0] & ~cs_n & ~we_n;   //0x1
assign baud_cs2 = ~A[4] & ~A[3] & ~A[2] & A[1] & ~A[0] & ~cs_n & ~we_n;   //0x2
assign baud_cs3 = ~A[4] & ~A[3] & ~A[2] & A[1] & A[0] & ~cs_n & ~we_n;    //0x3

assign inter_pos0 = ~A[4] & ~A[3] & A[2] & ~A[1] & ~A[0] & ~cs_n & ~oe_n; //0x4 读出中断位置
assign inter_pos1 = ~A[4] & ~A[3] & A[2] & ~A[1] & A[0] & ~cs_n & ~oe_n;  //0x5
assign inter_pos2 = ~A[4] & ~A[3] & A[2] & A[1] & ~A[0] & ~cs_n & ~oe_n;  //0x6
assign inter_pos3 = ~A[4] & ~A[3] & A[2] & A[1] & A[0] & ~cs_n & ~oe_n;   //0x7
assign inter_pos4 = ~A[4] & A[3] & ~A[2] & ~A[1] & ~A[0] & ~cs_n & ~oe_n; //0x8
assign inter_pos5 = ~A[4] & A[3] & ~A[2] & ~A[1] & A[0] & ~cs_n & ~oe_n;  //0x9
assign inter_pos6 = ~A[4] & A[3] & ~A[2] & A[1] & ~A[0] & ~cs_n & ~oe_n;  //0xa
assign inter_pos7 = ~A[4] & A[3] & ~A[2] & A[1] & A[0] & ~cs_n & ~oe_n;   //0xb

assign inter_mask = ~A[4] & A[3] & A[2] & ~A[1] & ~A[0] & ~cs_n & ~we_n;  //0xc 中断使能

assign fifot0_cs = A[4] & ~A[3] & ~A[2] & ~A[1] & ~A[0] & ~cs_n & ~we_n;  //0x10
assign fifot1_cs = A[4] & ~A[3] & ~A[2] & ~A[1] & A[0] & ~cs_n & ~we_n;   //0x11
assign fifot2_cs = A[4] & ~A[3] & ~A[2] & A[1] & ~A[0] & ~cs_n & ~we_n;   //0x12
assign fifot3_cs = A[4] & ~A[3] & ~A[2] & A[1] & A[0] & ~cs_n & ~we_n;    //0x13
assign fifor0_cs = A[4] & ~A[3] & A[2] & ~A[1] & ~A[0] & ~cs_n & ~oe_n;   //0x14
assign fifor1_cs = A[4] & ~A[3] & A[2] & ~A[1] & A[0] & ~cs_n & ~oe_n;    //0x15
assign fifor2_cs = A[4] & ~A[3] & A[2] & A[1] & ~A[0] & ~cs_n & ~oe_n;    //0x16
assign fifor3_cs = A[4] & ~A[3] & A[2] & A[1] & A[0] & ~cs_n & ~oe_n;     //0x17

endmodule