uart4.plg

来自「一个UART的FPGA core」· PLG 代码 · 共 17 行

@P:  Worst Slack : 492.792
@P:  Uart4|clk - Estimated Frequency : 69.4 MHz
@P:  Uart4|clk - Requested Frequency : 1.0 MHz
@P:  Uart4|clk - Estimated Period : 14.417
@P:  Uart4|clk - Requested Period : 1000.000
@P:  Uart4|clk - Slack : 492.792
@P:  Uart4|clk_in - Estimated Frequency : 106.3 MHz
@P:  Uart4|clk_in - Requested Frequency : 1.0 MHz
@P:  Uart4|clk_in - Estimated Period : 9.403
@P:  Uart4|clk_in - Requested Period : 1000.000
@P:  Uart4|clk_in - Slack : 990.597
@P:  System - Estimated Frequency : 143.4 MHz
@P:  System - Requested Frequency : 1.0 MHz
@P:  System - Estimated Period : 6.973
@P:  System - Requested Period : 1000.000
@P:  System - Slack : 993.027