uart.twr

一个UART的FPGA core

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Lattice TRACE Report, Version ispLever_v51_SP2_Build (10)
Fri Jul 07 14:18:49 2006

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2006 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
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Command line:    trce.exe -v 1 -o uart.twr uart.ncd uart.prf 
Design file:     uart.ncd
Preference file: uart.prf
Device,speed:    LCMXO640C,3
Report level:    verbose report, limited to 1 item per preference
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BLOCK ASYNCPATHS
BLOCK RESETPATHS
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================================================================================
Preference: FREQUENCY PORT "clk" 50.000000 MHz ;
            2773 items scored, 0 timing errors detected.
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WARNING - trce: Clock skew between net 'baud_clk1_c' and net 'clk_c' not
          computed: nets may not be related 
WARNING - trce: Clock skew between net 'baud_clk_c' and net 'clk_c' not
          computed: nets may not be related 
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Passed:  The following path meets requirements by 2.062ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FF         Q              u12/intmask_2__Q  (from clk_c -)
   Destination:    FF         Data in        u12/int_reg_Q  (to clk_c +)

   Delay:               7.757ns  (27.0% logic, 73.0% route), 5 logic levels.

 Constraint Details:

       7.757ns physical path delay SLICE_283 to u12/SLICE_122 meets
      10.000ns delay constraint less
       0.000ns skew and 
       0.181ns DIN_SET requirement (totaling 9.819ns) by 2.062ns

 Physical Path Details:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.613      R3C5A.CLK to       R3C5A.Q0 SLICE_283 (from clk_c)
ROUTE         1     3.580       R3C5A.Q0 to       R4C5C.B1 u12/intmask_2
CTOF_DEL    ---     0.371       R4C5C.B1 to       R4C5C.F1 SLICE_287
ROUTE         1     0.497       R4C5C.F1 to       R4C5C.C0 u12/fifot2_intZ0
CTOF_DEL    ---     0.371       R4C5C.C0 to       R4C5C.F0 SLICE_287
ROUTE         1     1.086       R4C5C.F0 to       R5C5D.B1 u12/int_regsrZ0Z_2
CTOF_DEL    ---     0.371       R5C5D.B1 to       R5C5D.F1 u12/SLICE_122
ROUTE         1     0.497       R5C5D.F1 to       R5C5D.C0 u12/int_regs_iZ0
CTOF_DEL    ---     0.371       R5C5D.C0 to       R5C5D.F0 u12/SLICE_122
ROUTE         1     0.000       R5C5D.F0 to      R5C5D.DI0 u12/Q_0 (to clk_c)
                  --------
                    7.757   (27.0% logic, 73.0% route), 5 logic levels.

 Clock Skew Details: 

 Source Clock: 
           Delay              Connection
          1.425ns         58.PADDI to R3C5A.CLK       

 Destination Clock :
           Delay              Connection
          1.425ns         58.PADDI to R5C5D.CLK       

Report:   62.988MHz is the maximum frequency for this preference.

Report Summary
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----------------------------------------------------------------------------
Preference                              |   Constraint|       Actual|Levels
----------------------------------------------------------------------------
                                        |             |             |
FREQUENCY PORT "clk" 50.000000 MHz ;    |   50.000 MHz|   62.988 MHz|     5
                                        |             |             |
----------------------------------------------------------------------------


All preferences were met.


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 2773 paths, 1 nets, and 1694 connections (60.0% coverage)

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