uart4.vhm

一个UART的FPGA core

--
-- Written by Synplicity
-- Fri Jul 07 14:16:33 2006
--

-- No definition of black box LUCENT.CCU2.PRIM
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity DPR16X2B is
port(
  RDO0 :  out std_logic;
  RDO1 :  out std_logic;
  WDO0 :  out std_logic;
  WDO1 :  out std_logic;
  RAD0 :  in std_logic;
  RAD1 :  in std_logic;
  RAD2 :  in std_logic;
  RAD3 :  in std_logic;
  WAD0 :  in std_logic;
  WAD1 :  in std_logic;
  WAD2 :  in std_logic;
  WAD3 :  in std_logic;
  DI0 :  in std_logic;
  DI1 :  in std_logic;
  WRE :  in std_logic;
  WCK :  in std_logic;
  GSR :  in std_logic);
end DPR16X2B;

architecture beh of DPR16X2B is
  signal UN1_WADR_REG : std_logic_vector (3 downto 0);
  signal WADR_REG : std_logic_vector (3 downto 0);
  signal DIN_REG_4 : std_logic_vector (1 downto 0);
  signal DIN_REG : std_logic_vector (1 downto 0);
  signal \UN1_MEM_15_\ : std_logic_vector (1 downto 0);
  signal \MEM_15_\ : std_logic_vector (1 downto 0);
  signal \UN1_MEM_5_\ : std_logic_vector (1 downto 0);
  signal \MEM_5_\ : std_logic_vector (1 downto 0);
  signal \UN1_MEM_9_\ : std_logic_vector (1 downto 0);
  signal \MEM_9_\ : std_logic_vector (1 downto 0);
  signal \UN1_MEM_11_\ : std_logic_vector (1 downto 0);
  signal \MEM_11_\ : std_logic_vector (1 downto 0);
  signal \UN1_MEM_0_\ : std_logic_vector (1 downto 0);
  signal \MEM_0_\ : std_logic_vector (1 downto 0);
  signal \UN1_MEM_12_\ : std_logic_vector (1 downto 0);
  signal \MEM_12_\ : std_logic_vector (1 downto 0);
  signal \UN1_MEM_14_\ : std_logic_vector (1 downto 0);
  signal \MEM_14_\ : std_logic_vector (1 downto 0);
  signal \UN1_MEM_10_\ : std_logic_vector (1 downto 0);
  signal \MEM_10_\ : std_logic_vector (1 downto 0);
  signal \UN1_MEM_4_\ : std_logic_vector (1 downto 0);
  signal \MEM_4_\ : std_logic_vector (1 downto 0);
  signal \UN1_MEM_8_\ : std_logic_vector (1 downto 0);
  signal \MEM_8_\ : std_logic_vector (1 downto 0);
  signal \UN1_MEM_13_\ : std_logic_vector (1 downto 0);
  signal \MEM_13_\ : std_logic_vector (1 downto 0);
  signal \UN1_MEM_6_\ : std_logic_vector (1 downto 0);
  signal \MEM_6_\ : std_logic_vector (1 downto 0);
  signal \UN1_MEM_2_\ : std_logic_vector (1 downto 0);
  signal \MEM_2_\ : std_logic_vector (1 downto 0);
  signal \UN1_MEM_3_\ : std_logic_vector (1 downto 0);
  signal \MEM_3_\ : std_logic_vector (1 downto 0);
  signal \UN1_MEM_7_\ : std_logic_vector (1 downto 0);
  signal \MEM_7_\ : std_logic_vector (1 downto 0);
  signal \UN1_MEM_1_\ : std_logic_vector (1 downto 0);
  signal \MEM_1_\ : std_logic_vector (1 downto 0);
  signal RDOB : std_logic_vector (1 downto 0);
  signal WDOB : std_logic_vector (1 downto 0);
  signal UN1_GSR : std_logic ;
  signal WAD0B : std_logic ;
  signal WAD1B : std_logic ;
  signal WAD2B : std_logic ;
  signal WAD3B : std_logic ;
  signal DI0B : std_logic ;
  signal DI1B : std_logic ;
  signal WCKB : std_logic ;
  signal WREB : std_logic ;
  signal RAD0B : std_logic ;
  signal RAD1B : std_logic ;
  signal RAD2B : std_logic ;
  signal RAD3B : std_logic ;
  signal UN1_WAD0B : std_logic ;
  signal UN1_WAD1B : std_logic ;
  signal UN1_WAD2B : std_logic ;
  signal UN1_WAD3B : std_logic ;
  signal UN1_WCKB : std_logic ;
  signal UN1_RAD0B : std_logic ;
  signal UN1_RAD1B : std_logic ;
  signal UN1_RAD2B : std_logic ;
  signal UN1_RAD3B : std_logic ;
  signal WRE_REG : std_logic ;
  signal UN1_WADR_REG_1 : std_logic ;
  signal UN1_WADR_REG_2 : std_logic ;
  signal UN1_WADR_REG_3 : std_logic ;
  signal UN1_WADR_REG_4 : std_logic ;
  signal UN1_WADR_REG_5 : std_logic ;
  signal UN1_WADR_REG_6 : std_logic ;
  signal UN1_WADR_REG_7 : std_logic ;
  signal UN1_WADR_REG_8 : std_logic ;
  signal UN1_WADR_REG_9 : std_logic ;
  signal UN1_WADR_REG_10 : std_logic ;
  signal UN1_WADR_REG_11 : std_logic ;
  signal UN1_WADR_REG_12 : std_logic ;
  signal UN1_WADR_REG_13 : std_logic ;
  signal UN1_WADR_REG_14 : std_logic ;
  signal UN1_WADR_REG_15 : std_logic ;
  signal UN1_WADR_REG_16 : std_logic ;
  signal UN1_RAD0B_1 : std_logic ;
  signal UN1_WAD0B_1 : std_logic ;
  signal UN1_RAD0B_2 : std_logic ;
  signal UN1_RAD0B_3 : std_logic ;
  signal UN1_RAD1B_1 : std_logic ;
  signal UN1_RAD0B_4 : std_logic ;
  signal UN1_RAD2B_1 : std_logic ;
  signal UN1_RAD0B_5 : std_logic ;
  signal UN1_RAD1B_2 : std_logic ;
  signal UN1_RAD0B_6 : std_logic ;
  signal UN1_RAD3B_1 : std_logic ;
  signal UN1_RAD0B_7 : std_logic ;
  signal UN1_RAD1B_3 : std_logic ;
  signal UN1_RAD0B_8 : std_logic ;
  signal UN1_RAD2B_2 : std_logic ;
  signal UN1_RAD0B_9 : std_logic ;
  signal UN1_RAD1B_4 : std_logic ;
  signal UN1_WAD0B_2 : std_logic ;
  signal UN1_WAD0B_3 : std_logic ;
  signal UN1_WAD1B_1 : std_logic ;
  signal UN1_WAD0B_4 : std_logic ;
  signal UN1_WAD2B_1 : std_logic ;
  signal UN1_WAD0B_5 : std_logic ;
  signal UN1_WAD1B_2 : std_logic ;
  signal UN1_WAD0B_6 : std_logic ;
  signal UN1_WAD3B_1 : std_logic ;
  signal UN1_WAD0B_7 : std_logic ;
  signal UN1_WAD1B_3 : std_logic ;
  signal UN1_WAD0B_8 : std_logic ;
  signal UN1_WAD2B_2 : std_logic ;
  signal UN1_WAD0B_9 : std_logic ;
  signal UN1_WAD1B_4 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  UN1_GSR <= not GSR;
  UN1_WADR_REG(0) <= not WADR_REG(0);
  UN1_WADR_REG(1) <= not WADR_REG(1);
  UN1_WADR_REG(2) <= not WADR_REG(2);
  UN1_WADR_REG(3) <= not WADR_REG(3);
  WAD0B <= WAD0;
  WAD1B <= WAD1;
  WAD2B <= WAD2;
  WAD3B <= WAD3;
  DI0B <= DI0;
  DI1B <= DI1;
  WCKB <= WCK;
  WREB <= WRE;
  RAD0B <= RAD0;
  RAD1B <= RAD1;
  RAD2B <= RAD2;
  RAD3B <= RAD3;
  UN1_WAD0B <= not WAD0B;
  UN1_WAD1B <= not WAD1B;
  UN1_WAD2B <= not WAD2B;
  UN1_WAD3B <= not WAD3B;
  UN1_WCKB <= not WCKB;
  UN1_RAD0B <= not RAD0B;
  UN1_RAD1B <= not RAD1B;
  UN1_RAD2B <= not RAD2B;
  UN1_RAD3B <= not RAD3B;
  II_wre_reg: prim_dff port map (WRE_REG, WREB, WCKB, UN1_GSR, '0');
  UN1_WADR_REG_1 <= WADR_REG(0) and WADR_REG(1) and WADR_REG(2) and WADR_REG(3) and WRE_REG  after 100 ps;
  UN1_WADR_REG_2 <= UN1_WADR_REG(0) and UN1_WADR_REG(1) and UN1_WADR_REG(2) and UN1_WADR_REG(3) and WRE_REG  after 100 ps;
  UN1_WADR_REG_3 <= WADR_REG(1) and UN1_WADR_REG(0) and UN1_WADR_REG(2) and UN1_WADR_REG(3) and WRE_REG  after 100 ps;
  UN1_WADR_REG_4 <= WADR_REG(0) and WADR_REG(1) and UN1_WADR_REG(2) and UN1_WADR_REG(3) and WRE_REG  after 100 ps;
  UN1_WADR_REG_5 <= WADR_REG(0) and WADR_REG(1) and WADR_REG(2) and UN1_WADR_REG(3) and WRE_REG  after 100 ps;
  UN1_WADR_REG_6 <= WADR_REG(2) and UN1_WADR_REG(0) and UN1_WADR_REG(1) and UN1_WADR_REG(3) and WRE_REG  after 100 ps;
  UN1_WADR_REG_7 <= WADR_REG(0) and UN1_WADR_REG(1) and UN1_WADR_REG(2) and UN1_WADR_REG(3) and WRE_REG  after 100 ps;
  UN1_WADR_REG_8 <= WADR_REG(1) and WADR_REG(2) and UN1_WADR_REG(0) and UN1_WADR_REG(3) and WRE_REG  after 100 ps;
  UN1_WADR_REG_9 <= WADR_REG(0) and WADR_REG(1) and WADR_REG(3) and UN1_WADR_REG(2) and WRE_REG  after 100 ps;
  UN1_WADR_REG_10 <= WADR_REG(3) and UN1_WADR_REG(0) and UN1_WADR_REG(1) and UN1_WADR_REG(2) and WRE_REG  after 100 ps;
  UN1_WADR_REG_11 <= WADR_REG(0) and WADR_REG(2) and UN1_WADR_REG(1) and UN1_WADR_REG(3) and WRE_REG  after 100 ps;
  UN1_WADR_REG_12 <= WADR_REG(1) and WADR_REG(3) and UN1_WADR_REG(0) and UN1_WADR_REG(2) and WRE_REG  after 100 ps;
  UN1_WADR_REG_13 <= WADR_REG(1) and WADR_REG(2) and WADR_REG(3) and UN1_WADR_REG(0) and WRE_REG  after 100 ps;
  UN1_WADR_REG_14 <= WADR_REG(2) and WADR_REG(3) and UN1_WADR_REG(0) and UN1_WADR_REG(1) and WRE_REG  after 100 ps;
  UN1_WADR_REG_15 <= WADR_REG(0) and WADR_REG(3) and UN1_WADR_REG(1) and UN1_WADR_REG(2) and WRE_REG  after 100 ps;
  UN1_WADR_REG_16 <= WADR_REG(0) and WADR_REG(2) and WADR_REG(3) and UN1_WADR_REG(1) and WRE_REG  after 100 ps;
  UN1_RAD0B_1 <= RAD0B and RAD1B and RAD2B and RAD3B  after 100 ps;
  UN1_WAD0B_1 <= WAD0B and WAD1B and WAD2B and WAD3B  after 100 ps;
  DIN_REG_4(0) <= DIN_REG(0) after 100 ps when GSR = '0' else DI0B after 100 ps;
  DIN_REG_4(1) <= DIN_REG(1) after 100 ps when GSR = '0' else DI1B after 100 ps;
  UN1_RAD0B_2 <= UN1_RAD0B and UN1_RAD1B and UN1_RAD2B and UN1_RAD3B  after 100 ps;
  UN1_RAD0B_3 <= RAD0B and UN1_RAD1B and UN1_RAD2B and UN1_RAD3B  after 100 ps;
  UN1_RAD1B_1 <= RAD1B and UN1_RAD0B and UN1_RAD2B and UN1_RAD3B  after 100 ps;
  UN1_RAD0B_4 <= RAD0B and RAD1B and UN1_RAD2B and UN1_RAD3B  after 100 ps;
  UN1_RAD2B_1 <= RAD2B and UN1_RAD0B and UN1_RAD1B and UN1_RAD3B  after 100 ps;
  UN1_RAD0B_5 <= RAD0B and RAD2B and UN1_RAD1B and UN1_RAD3B  after 100 ps;
  UN1_RAD1B_2 <= RAD1B and RAD2B and UN1_RAD0B and UN1_RAD3B  after 100 ps;
  UN1_RAD0B_6 <= RAD0B and RAD1B and RAD2B and UN1_RAD3B  after 100 ps;
  UN1_RAD3B_1 <= RAD3B and UN1_RAD0B and UN1_RAD1B and UN1_RAD2B  after 100 ps;
  UN1_RAD0B_7 <= RAD0B and RAD3B and UN1_RAD1B and UN1_RAD2B  after 100 ps;
  UN1_RAD1B_3 <= RAD1B and RAD3B and UN1_RAD0B and UN1_RAD2B  after 100 ps;
  UN1_RAD0B_8 <= RAD0B and RAD1B and RAD3B and UN1_RAD2B  after 100 ps;
  UN1_RAD2B_2 <= RAD2B and RAD3B and UN1_RAD0B and UN1_RAD1B  after 100 ps;
  UN1_RAD0B_9 <= RAD0B and RAD2B and RAD3B and UN1_RAD1B  after 100 ps;
  UN1_RAD1B_4 <= RAD1B and RAD2B and RAD3B and UN1_RAD0B  after 100 ps;
  UN1_WAD0B_2 <= UN1_WAD0B and UN1_WAD1B and UN1_WAD2B and UN1_WAD3B  after 100 ps;
  UN1_WAD0B_3 <= WAD0B and UN1_WAD1B and UN1_WAD2B and UN1_WAD3B  after 100 ps;
  UN1_WAD1B_1 <= WAD1B and UN1_WAD0B and UN1_WAD2B and UN1_WAD3B  after 100 ps;
  UN1_WAD0B_4 <= WAD0B and WAD1B and UN1_WAD2B and UN1_WAD3B  after 100 ps;
  UN1_WAD2B_1 <= WAD2B and UN1_WAD0B and UN1_WAD1B and UN1_WAD3B  after 100 ps;
  UN1_WAD0B_5 <= WAD0B and WAD2B and UN1_WAD1B and UN1_WAD3B  after 100 ps;
  UN1_WAD1B_2 <= WAD1B and WAD2B and UN1_WAD0B and UN1_WAD3B  after 100 ps;
  UN1_WAD0B_6 <= WAD0B and WAD1B and WAD2B and UN1_WAD3B  after 100 ps;
  UN1_WAD3B_1 <= WAD3B and UN1_WAD0B and UN1_WAD1B and UN1_WAD2B  after 100 ps;
  UN1_WAD0B_7 <= WAD0B and WAD3B and UN1_WAD1B and UN1_WAD2B  after 100 ps;
  UN1_WAD1B_3 <= WAD1B and WAD3B and UN1_WAD0B and UN1_WAD2B  after 100 ps;
  UN1_WAD0B_8 <= WAD0B and WAD1B and WAD3B and UN1_WAD2B  after 100 ps;
  UN1_WAD2B_2 <= WAD2B and WAD3B and UN1_WAD0B and UN1_WAD1B  after 100 ps;
  UN1_WAD0B_9 <= WAD0B and WAD2B and WAD3B and UN1_WAD1B  after 100 ps;
  UN1_WAD1B_4 <= WAD1B and WAD2B and WAD3B and UN1_WAD0B  after 100 ps;
  \UN1_MEM_15_\(0) <= \MEM_15_\(0) after 100 ps when UN1_WADR_REG_1 = '0' else DIN_REG(0) after 100 ps;
  \UN1_MEM_15_\(1) <= \MEM_15_\(1) after 100 ps when UN1_WADR_REG_1 = '0' else DIN_REG(1) after 100 ps;
  \UN1_MEM_5_\(0) <= \MEM_5_\(0) after 100 ps when UN1_WADR_REG_11 = '0' else DIN_REG(0) after 100 ps;
  \UN1_MEM_5_\(1) <= \MEM_5_\(1) after 100 ps when UN1_WADR_REG_11 = '0' else DIN_REG(1) after 100 ps;
  \UN1_MEM_9_\(0) <= \MEM_9_\(0) after 100 ps when UN1_WADR_REG_15 = '0' else DIN_REG(0) after 100 ps;
  \UN1_MEM_9_\(1) <= \MEM_9_\(1) after 100 ps when UN1_WADR_REG_15 = '0' else DIN_REG(1) after 100 ps;
  \UN1_MEM_11_\(0) <= \MEM_11_\(0) after 100 ps when UN1_WADR_REG_9 = '0' else DIN_REG(0) after 100 ps;
  \UN1_MEM_11_\(1) <= \MEM_11_\(1) after 100 ps when UN1_WADR_REG_9 = '0' else DIN_REG(1) after 100 ps;
  \UN1_MEM_0_\(0) <= \MEM_0_\(0) after 100 ps when UN1_WADR_REG_2 = '0' else DIN_REG(0) after 100 ps;
  \UN1_MEM_0_\(1) <= \MEM_0_\(1) after 100 ps when UN1_WADR_REG_2 = '0' else DIN_REG(1) after 100 ps;
  \UN1_MEM_12_\(0) <= \MEM_12_\(0) after 100 ps when UN1_WADR_REG_14 = '0' else DIN_REG(0) after 100 ps;
  \UN1_MEM_12_\(1) <= \MEM_12_\(1) after 100 ps when UN1_WADR_REG_14 = '0' else DIN_REG(1) after 100 ps;
  \UN1_MEM_14_\(0) <= \MEM_14_\(0) after 100 ps when UN1_WADR_REG_13 = '0' else DIN_REG(0) after 100 ps;
  \UN1_MEM_14_\(1) <= \MEM_14_\(1) after 100 ps when UN1_WADR_REG_13 = '0' else DIN_REG(1) after 100 ps;
  \UN1_MEM_10_\(0) <= \MEM_10_\(0) after 100 ps when UN1_WADR_REG_12 = '0' else DIN_REG(0) after 100 ps;
  \UN1_MEM_10_\(1) <= \MEM_10_\(1) after 100 ps when UN1_WADR_REG_12 = '0' else DIN_REG(1) after 100 ps;
  \UN1_MEM_4_\(0) <= \MEM_4_\(0) after 100 ps when UN1_WADR_REG_6 = '0' else DIN_REG(0) after 100 ps;
  \UN1_MEM_4_\(1) <= \MEM_4_\(1) after 100 ps when UN1_WADR_REG_6 = '0' else DIN_REG(1) after 100 ps;
  \UN1_MEM_8_\(0) <= \MEM_8_\(0) after 100 ps when UN1_WADR_REG_10 = '0' else DIN_REG(0) after 100 ps;
  \UN1_MEM_8_\(1) <= \MEM_8_\(1) after 100 ps when UN1_WADR_REG_10 = '0' else DIN_REG(1) after 100 ps;
  \UN1_MEM_13_\(0) <= \MEM_13_\(0) after 100 ps when UN1_WADR_REG_16 = '0' else DIN_REG(0) after 100 ps;
  \UN1_MEM_13_\(1) <= \MEM_13_\(1) after 100 ps when UN1_WADR_REG_16 = '0' else DIN_REG(1) after 100 ps;
  \UN1_MEM_6_\(0) <= \MEM_6_\(0) after 100 ps when UN1_WADR_REG_8 = '0' else DIN_REG(0) after 100 ps;
  \UN1_MEM_6_\(1) <= \MEM_6_\(1) after 100 ps when UN1_WADR_REG_8 = '0' else DIN_REG(1) after 100 ps;
  \UN1_MEM_2_\(0) <= \MEM_2_\(0) after 100 ps when UN1_WADR_REG_3 = '0' else DIN_REG(0) after 100 ps;
  \UN1_MEM_2_\(1) <= \MEM_2_\(1) after 100 ps when UN1_WADR_REG_3 = '0' else DIN_REG(1) after 100 ps;
  \UN1_MEM_3_\(0) <= \MEM_3_\(0) after 100 ps when UN1_WADR_REG_4 = '0' else DIN_REG(0) after 100 ps;
  \UN1_MEM_3_\(1) <= \MEM_3_\(1) after 100 ps when UN1_WADR_REG_4 = '0' else DIN_REG(1) after 100 ps;
  \UN1_MEM_7_\(0) <= \MEM_7_\(0) after 100 ps when UN1_WADR_REG_5 = '0' else DIN_REG(0) after 100 ps;
  \UN1_MEM_7_\(1) <= \MEM_7_\(1) after 100 ps when UN1_WADR_REG_5 = '0' else DIN_REG(1) after 100 ps;
  \UN1_MEM_1_\(0) <= \MEM_1_\(0) after 100 ps when UN1_WADR_REG_7 = '0' else DIN_REG(0) after 100 ps;
  \UN1_MEM_1_\(1) <= \MEM_1_\(1) after 100 ps when UN1_WADR_REG_7 = '0' else DIN_REG(1) after 100 ps;
  RDOB(0) <= 
	  (UN1_RAD0B_2 and \MEM_0_\(0) ) or 
	  (UN1_RAD0B_3 and \MEM_1_\(0) ) or 
	  (UN1_RAD1B_1 and \MEM_2_\(0) ) or 
	  (UN1_RAD0B_4 and \MEM_3_\(0) ) or 
	  (UN1_RAD2B_1 and \MEM_4_\(0) ) or 
	  (UN1_RAD0B_5 and \MEM_5_\(0) ) or 
	  (UN1_RAD1B_2 and \MEM_6_\(0) ) or 
	  (UN1_RAD0B_6 and \MEM_7_\(0) ) or 
	  (UN1_RAD3B_1 and \MEM_8_\(0) ) or 
	  (UN1_RAD0B_7 and \MEM_9_\(0) ) or 
	  (UN1_RAD1B_3 and \MEM_10_\(0) ) or 
	  (UN1_RAD0B_8 and \MEM_11_\(0) ) or 
	  (UN1_RAD2B_2 and \MEM_12_\(0) ) or 
	  (UN1_RAD0B_9 and \MEM_13_\(0) ) or 
	  (UN1_RAD1B_4 and \MEM_14_\(0) ) or 
	  (UN1_RAD0B_1 and \MEM_15_\(0) ) after 100 ps;
  RDOB(1) <= 
	  (UN1_RAD0B_2 and \MEM_0_\(1) ) or 
	  (UN1_RAD0B_3 and \MEM_1_\(1) ) or 
	  (UN1_RAD1B_1 and \MEM_2_\(1) ) or 
	  (UN1_RAD0B_4 and \MEM_3_\(1) ) or 
	  (UN1_RAD2B_1 and \MEM_4_\(1) ) or 
	  (UN1_RAD0B_5 and \MEM_5_\(1) ) or 
	  (UN1_RAD1B_2 and \MEM_6_\(1) ) or 
	  (UN1_RAD0B_6 and \MEM_7_\(1) ) or 
	  (UN1_RAD3B_1 and \MEM_8_\(1) ) or 
	  (UN1_RAD0B_7 and \MEM_9_\(1) ) or 
	  (UN1_RAD1B_3 and \MEM_10_\(1) ) or 
	  (UN1_RAD0B_8 and \MEM_11_\(1) ) or 
	  (UN1_RAD2B_2 and \MEM_12_\(1) ) or 
	  (UN1_RAD0B_9 and \MEM_13_\(1) ) or 
	  (UN1_RAD1B_4 and \MEM_14_\(1) ) or 
	  (UN1_RAD0B_1 and \MEM_15_\(1) ) after 100 ps;
  WDOB(0) <= 
	  (UN1_WAD0B_2 and \MEM_0_\(0) ) or 
	  (UN1_WAD0B_3 and \MEM_1_\(0) ) or 
	  (UN1_WAD1B_1 and \MEM_2_\(0) ) or 
	  (UN1_WAD0B_4 and \MEM_3_\(0) ) or 
	  (UN1_WAD2B_1 and \MEM_4_\(0) ) or 
	  (UN1_WAD0B_5 and \MEM_5_\(0) ) or 
	  (UN1_WAD1B_2 and \MEM_6_\(0) ) or 
	  (UN1_WAD0B_6 and \MEM_7_\(0) ) or 
	  (UN1_WAD3B_1 and \MEM_8_\(0) ) or 
	  (UN1_WAD0B_7 and \MEM_9_\(0) ) or 
	  (UN1_WAD1B_3 and \MEM_10_\(0) ) or 
	  (UN1_WAD0B_8 and \MEM_11_\(0) ) or 
	  (UN1_WAD2B_2 and \MEM_12_\(0) ) or 
	  (UN1_WAD0B_9 and \MEM_13_\(0) ) or 
	  (UN1_WAD1B_4 and \MEM_14_\(0) ) or 
	  (UN1_WAD0B_1 and \MEM_15_\(0) ) after 100 ps;
  WDOB(1) <= 
	  (UN1_WAD0B_2 and \MEM_0_\(1) ) or 
	  (UN1_WAD0B_3 and \MEM_1_\(1) ) or 
	  (UN1_WAD1B_1 and \MEM_2_\(1) ) or 
	  (UN1_WAD0B_4 and \MEM_3_\(1) ) or 
	  (UN1_WAD2B_1 and \MEM_4_\(1) ) or 
	  (UN1_WAD0B_5 and \MEM_5_\(1) ) or 
	  (UN1_WAD1B_2 and \MEM_6_\(1) ) or 
	  (UN1_WAD0B_6 and \MEM_7_\(1) ) or 
	  (UN1_WAD3B_1 and \MEM_8_\(1) ) or 
	  (UN1_WAD0B_7 and \MEM_9_\(1) ) or 
	  (UN1_WAD1B_3 and \MEM_10_\(1) ) or 
	  (UN1_WAD0B_8 and \MEM_11_\(1) ) or 
	  (UN1_WAD2B_2 and \MEM_12_\(1) ) or 
	  (UN1_WAD0B_9 and \MEM_13_\(1) ) or 
	  (UN1_WAD1B_4 and \MEM_14_\(1) ) or 
	  (UN1_WAD0B_1 and \MEM_15_\(1) ) after 100 ps;
  WDO0 <= WDOB(0);
  WDO1 <= WDOB(1);
  RDO0 <= RDOB(0);
  RDO1 <= RDOB(1);
  \II_MEM_14_[0]\: prim_dff port map (\MEM_14_\(0), \UN1_MEM_14_\(0), UN1_WCKB, '0', '0');
  \II_MEM_14_[1]\: prim_dff port map (\MEM_14_\(1), \UN1_MEM_14_\(1), UN1_WCKB, '0', '0');
  \II_MEM_13_[0]\: prim_dff port map (\MEM_13_\(0), \UN1_MEM_13_\(0), UN1_WCKB, '0', '0');
  \II_MEM_13_[1]\: prim_dff port map (\MEM_13_\(1), \UN1_MEM_13_\(1), UN1_WCKB, '0', '0');
  \II_MEM_12_[0]\: prim_dff port map (\MEM_12_\(0), \UN1_MEM_12_\(0), UN1_WCKB, '0', '0');
  \II_MEM_12_[1]\: prim_dff port map (\MEM_12_\(1), \UN1_MEM_12_\(1), UN1_WCKB, '0', '0');
  \II_MEM_11_[0]\: prim_dff port map (\MEM_11_\(0), \UN1_MEM_11_\(0), UN1_WCKB, '0', '0');
  \II_MEM_11_[1]\: prim_dff port map (\MEM_11_\(1), \UN1_MEM_11_\(1), UN1_WCKB, '0', '0');
  \II_MEM_10_[0]\: prim_dff port map (\MEM_10_\(0), \UN1_MEM_10_\(0), UN1_WCKB, '0', '0');
  \II_MEM_10_[1]\: prim_dff port map (\MEM_10_\(1), \UN1_MEM_10_\(1), UN1_WCKB, '0', '0');
  \II_MEM_9_[0]\: prim_dff port map (\MEM_9_\(0), \UN1_MEM_9_\(0), UN1_WCKB, '0', '0');
  \II_MEM_9_[1]\: prim_dff port map (\MEM_9_\(1), \UN1_MEM_9_\(1), UN1_WCKB, '0', '0');
  \II_MEM_8_[0]\: prim_dff port map (\MEM_8_\(0), \UN1_MEM_8_\(0), UN1_WCKB, '0', '0');
  \II_MEM_8_[1]\: prim_dff port map (\MEM_8_\(1), \UN1_MEM_8_\(1), UN1_WCKB, '0', '0');
  \II_MEM_7_[0]\: prim_dff port map (\MEM_7_\(0), \UN1_MEM_7_\(0), UN1_WCKB, '0', '0');
  \II_MEM_7_[1]\: prim_dff port map (\MEM_7_\(1), \UN1_MEM_7_\(1), UN1_WCKB, '0', '0');
  \II_MEM_6_[0]\: prim_dff port map (\MEM_6_\(0), \UN1_MEM_6_\(0), UN1_WCKB, '0', '0');
  \II_MEM_6_[1]\: prim_dff port map (\MEM_6_\(1), \UN1_MEM_6_\(1), UN1_WCKB, '0', '0');
  \II_MEM_5_[0]\: prim_dff port map (\MEM_5_\(0), \UN1_MEM_5_\(0), UN1_WCKB, '0', '0');
  \II_MEM_5_[1]\: prim_dff port map (\MEM_5_\(1), \UN1_MEM_5_\(1), UN1_WCKB, '0', '0');
  \II_MEM_4_[0]\: prim_dff port map (\MEM_4_\(0), \UN1_MEM_4_\(0), UN1_WCKB, '0', '0');
  \II_MEM_4_[1]\: prim_dff port map (\MEM_4_\(1), \UN1_MEM_4_\(1), UN1_WCKB, '0', '0');
  \II_MEM_3_[0]\: prim_dff port map (\MEM_3_\(0), \UN1_MEM_3_\(0), UN1_WCKB, '0', '0');
  \II_MEM_3_[1]\: prim_dff port map (\MEM_3_\(1), \UN1_MEM_3_\(1), UN1_WCKB, '0', '0');
  \II_MEM_2_[0]\: prim_dff port map (\MEM_2_\(0), \UN1_MEM_2_\(0), UN1_WCKB, '0', '0');
  \II_MEM_2_[1]\: prim_dff port map (\MEM_2_\(1), \UN1_MEM_2_\(1), UN1_WCKB, '0', '0');
  \II_MEM_1_[0]\: prim_dff port map (\MEM_1_\(0), \UN1_MEM_1_\(0), UN1_WCKB, '0', '0');
  \II_MEM_1_[1]\: prim_dff port map (\MEM_1_\(1), \UN1_MEM_1_\(1), UN1_WCKB, '0', '0');
  \II_MEM_0_[0]\: prim_dff port map (\MEM_0_\(0), \UN1_MEM_0_\(0), UN1_WCKB, '0', '0');
  \II_MEM_0_[1]\: prim_dff port map (\MEM_0_\(1), \UN1_MEM_0_\(1), UN1_WCKB, '0', '0');
  \II_MEM_15_[0]\: prim_dff port map (\MEM_15_\(0), \UN1_MEM_15_\(0), UN1_WCKB, '0', '0');
  \II_MEM_15_[1]\: prim_dff port map (\MEM_15_\(1), \UN1_MEM_15_\(1), UN1_WCKB, '0', '0');
  \II_din_reg[0]\: prim_dff port map (DIN_REG(0), DIN_REG_4(0), WCKB, '0', '0');
  \II_din_reg[1]\: prim_dff port map (DIN_REG(1), DIN_REG_4(1), WCKB, '0', '0');
  \II_wadr_reg[0]\: prim_dff port map (WADR_REG(0), WAD0B, WCKB, UN1_GSR, '0');
  \II_wadr_reg[1]\: prim_dff port map (WADR_REG(1), WAD1B, WCKB, UN1_GSR, '0');
  \II_wadr_reg[2]\: prim_dff port map (WADR_REG(2), WAD2B, WCKB, UN1_GSR, '0');
  \II_wadr_reg[3]\: prim_dff port map (WADR_REG(3), WAD3B, WCKB, UN1_GSR, '0');
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity BB is
port(
  B :  inout std_logic;
  I :  in std_logic;
  T :  in std_logic;
  O :  out std_logic);
end BB;

architecture beh of BB is
  signal TI : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  TI <= not T;
  B <= I after 100 ps when TI = '1' else 'Z' after 100 ps;
  O <= B;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity OB is
port(
  I :  in std_logic;
  O :  out std_logic);
end OB;

architecture beh of OB is
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  O <= I;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity IB is
port(
  I :  in std_logic;
  O :  out std_logic);
end IB;

architecture beh of IB is
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  O <= I;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;