uart4_top_tb.v

来自「一个UART的FPGA core」· Verilog 代码 · 共 69 行

`timescale 1ns/100ps
module uart4_top_tb;

reg  clk,rst;
reg [4:0] addr;
reg [7:0] data_in;
wire [7:0] data;
reg csn,we,oe;
reg [3:0] rxd;
wire inter;
wire [3:0] txd;

initial begin
clk <=0;
forever #10 clk <= !clk;
end

initial begin
rst <= 0 ;
#20 rst <= 1;
#20 rst <= 0;
end

initial
begin
addr <= 0;
#110 addr <= 12;
#20 addr <= 16;

end 

initial begin
   csn <= 1;
   #40 csn <= 0; 
end

initial begin
    we <= 0;
    #100 we <= 1 ;
    #400 we <= 0 ;
end

initial begin
    oe <= 0;
end

initial begin
   data_in <= 0;
   #110 data_in <= 1;
   #20 data_in <= 0;
   //forever #20 data_in <= data_in + 1; 
end

assign data = we ?  data_in : 8'bz;


Uart4 u0( .clk(clk),
          .rst(rst),
          .addr(addr),
          .data(data),
          .csn(csn),
          .inter(inter),
          .we(we),
          .oe(oe),
          .rxd(rxd),
          .txd(txd) );

endmodule