crc.fit.eqn

在quartus中用VHDL语言开发的crc校验

--C1_safe_q[11] is lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|safe_q[11] at LC_X1_Y11_N5
--operation mode is normal

C1_safe_q[11]_carry_eqn = C1L03;
C1_safe_q[11]_lut_out = C1_safe_q[11]_carry_eqn $ C1_safe_q[11];
C1_safe_q[11] = DFFEAS(C1_safe_q[11]_lut_out, GLOBAL(clk), !GLOBAL(start), , , , , , );


--C1_safe_q[10] is lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|safe_q[10] at LC_X1_Y11_N4
--operation mode is arithmetic

C1_safe_q[10]_carry_eqn = (!C1L61 & C1L72) # (C1L61 & C1L82);
C1_safe_q[10]_lut_out = C1_safe_q[10] $ !C1_safe_q[10]_carry_eqn;
C1_safe_q[10] = DFFEAS(C1_safe_q[10]_lut_out, GLOBAL(clk), !GLOBAL(start), , , , , , );

--C1L03 is lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|counter_cella10~COUT at LC_X1_Y11_N4
--operation mode is arithmetic

C1L03 = CARRY(C1_safe_q[10] & !C1L82);


--C1_safe_q[9] is lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|safe_q[9] at LC_X1_Y11_N3
--operation mode is arithmetic

C1_safe_q[9]_carry_eqn = (!C1L61 & C1L42) # (C1L61 & C1L52);
C1_safe_q[9]_lut_out = C1_safe_q[9] $ C1_safe_q[9]_carry_eqn;
C1_safe_q[9] = DFFEAS(C1_safe_q[9]_lut_out, GLOBAL(clk), !GLOBAL(start), , , , , , );

--C1L72 is lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|counter_cella9~COUT at LC_X1_Y11_N3
--operation mode is arithmetic

C1L72_cout_0 = !C1L42 # !C1_safe_q[9];
C1L72 = CARRY(C1L72_cout_0);

--C1L82 is lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|counter_cella9~COUTCOUT1_1 at LC_X1_Y11_N3
--operation mode is arithmetic

C1L82_cout_1 = !C1L52 # !C1_safe_q[9];
C1L82 = CARRY(C1L82_cout_1);


--C1_safe_q[8] is lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|safe_q[8] at LC_X1_Y11_N2
--operation mode is arithmetic

C1_safe_q[8]_carry_eqn = (!C1L61 & C1L12) # (C1L61 & C1L22);
C1_safe_q[8]_lut_out = C1_safe_q[8] $ (!C1_safe_q[8]_carry_eqn);
C1_safe_q[8] = DFFEAS(C1_safe_q[8]_lut_out, GLOBAL(clk), !GLOBAL(start), , , , , , );

--C1L42 is lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|counter_cella8~COUT at LC_X1_Y11_N2
--operation mode is arithmetic

C1L42_cout_0 = C1_safe_q[8] & !C1L12;
C1L42 = CARRY(C1L42_cout_0);

--C1L52 is lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|counter_cella8~COUTCOUT1_1 at LC_X1_Y11_N2
--operation mode is arithmetic

C1L52_cout_1 = C1_safe_q[8] & !C1L22;
C1L52 = CARRY(C1L52_cout_1);


--C1_safe_q[7] is lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|safe_q[7] at LC_X1_Y11_N1
--operation mode is arithmetic

C1_safe_q[7]_carry_eqn = (!C1L61 & C1L81) # (C1L61 & C1L91);
C1_safe_q[7]_lut_out = C1_safe_q[7] $ (C1_safe_q[7]_carry_eqn);
C1_safe_q[7] = DFFEAS(C1_safe_q[7]_lut_out, GLOBAL(clk), !GLOBAL(start), , , , , , );

--C1L12 is lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|counter_cella7~COUT at LC_X1_Y11_N1
--operation mode is arithmetic

C1L12_cout_0 = !C1L81 # !C1_safe_q[7];
C1L12 = CARRY(C1L12_cout_0);

--C1L22 is lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|counter_cella7~COUTCOUT1_1 at LC_X1_Y11_N1
--operation mode is arithmetic

C1L22_cout_1 = !C1L91 # !C1_safe_q[7];
C1L22 = CARRY(C1L22_cout_1);


--C1_safe_q[6] is lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|safe_q[6] at LC_X1_Y11_N0
--operation mode is arithmetic

C1_safe_q[6]_carry_eqn = C1L61;
C1_safe_q[6]_lut_out = C1_safe_q[6] $ !C1_safe_q[6]_carry_eqn;
C1_safe_q[6] = DFFEAS(C1_safe_q[6]_lut_out, GLOBAL(clk), !GLOBAL(start), , , , , , );

--C1L81 is lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|counter_cella6~COUT at LC_X1_Y11_N0
--operation mode is arithmetic

C1L81_cout_0 = C1_safe_q[6] & !C1L61;
C1L81 = CARRY(C1L81_cout_0);

--C1L91 is lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|counter_cella6~COUTCOUT1_1 at LC_X1_Y11_N0
--operation mode is arithmetic

C1L91_cout_1 = C1_safe_q[6] & !C1L61;
C1L91 = CARRY(C1L91_cout_1);


--C1_safe_q[5] is lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|safe_q[5] at LC_X1_Y12_N9
--operation mode is arithmetic

C1_safe_q[5]_carry_eqn = (!C1L2 & C1L31) # (C1L2 & C1L41);
C1_safe_q[5]_lut_out = C1_safe_q[5] $ (C1_safe_q[5]_carry_eqn);
C1_safe_q[5] = DFFEAS(C1_safe_q[5]_lut_out, GLOBAL(clk), !GLOBAL(start), , , , , , );

--C1L61 is lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|counter_cella5~COUT at LC_X1_Y12_N9
--operation mode is arithmetic

C1L61 = CARRY(!C1L41 # !C1_safe_q[5]);


--C1_safe_q[4] is lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|safe_q[4] at LC_X1_Y12_N8
--operation mode is arithmetic

C1_safe_q[4]_carry_eqn = (!C1L2 & C1L01) # (C1L2 & C1L11);
C1_safe_q[4]_lut_out = C1_safe_q[4] $ !C1_safe_q[4]_carry_eqn;
C1_safe_q[4] = DFFEAS(C1_safe_q[4]_lut_out, GLOBAL(clk), !GLOBAL(start), , , , , , );

--C1L31 is lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|counter_cella4~COUT at LC_X1_Y12_N8
--operation mode is arithmetic

C1L31_cout_0 = C1_safe_q[4] & !C1L01;
C1L31 = CARRY(C1L31_cout_0);

--C1L41 is lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|counter_cella4~COUTCOUT1_1 at LC_X1_Y12_N8
--operation mode is arithmetic

C1L41_cout_1 = C1_safe_q[4] & !C1L11;
C1L41 = CARRY(C1L41_cout_1);


--C1_safe_q[3] is lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|safe_q[3] at LC_X1_Y12_N7
--operation mode is arithmetic

C1_safe_q[3]_carry_eqn = (!C1L2 & C1L7) # (C1L2 & C1L8);
C1_safe_q[3]_lut_out = C1_safe_q[3] $ (C1_safe_q[3]_carry_eqn);
C1_safe_q[3] = DFFEAS(C1_safe_q[3]_lut_out, GLOBAL(clk), !GLOBAL(start), , , , , , );

--C1L01 is lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|counter_cella3~COUT at LC_X1_Y12_N7
--operation mode is arithmetic

C1L01_cout_0 = !C1L7 # !C1_safe_q[3];
C1L01 = CARRY(C1L01_cout_0);

--C1L11 is lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|counter_cella3~COUTCOUT1_1 at LC_X1_Y12_N7
--operation mode is arithmetic

C1L11_cout_1 = !C1L8 # !C1_safe_q[3];
C1L11 = CARRY(C1L11_cout_1);


--C1_safe_q[2] is lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|safe_q[2] at LC_X1_Y12_N6
--operation mode is arithmetic

C1_safe_q[2]_carry_eqn = (!C1L2 & C1L4) # (C1L2 & C1L5);
C1_safe_q[2]_lut_out = C1_safe_q[2] $ (!C1_safe_q[2]_carry_eqn);
C1_safe_q[2] = DFFEAS(C1_safe_q[2]_lut_out, GLOBAL(clk), !GLOBAL(start), , , , , , );

--C1L7 is lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|counter_cella2~COUT at LC_X1_Y12_N6
--operation mode is arithmetic

C1L7_cout_0 = C1_safe_q[2] & !C1L4;
C1L7 = CARRY(C1L7_cout_0);

--C1L8 is lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|counter_cella2~COUTCOUT1_1 at LC_X1_Y12_N6
--operation mode is arithmetic

C1L8_cout_1 = C1_safe_q[2] & !C1L5;
C1L8 = CARRY(C1L8_cout_1);


--C1_safe_q[1] is lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|safe_q[1] at LC_X1_Y12_N5
--operation mode is arithmetic

C1_safe_q[1]_carry_eqn = C1L2;
C1_safe_q[1]_lut_out = C1_safe_q[1] $ C1_safe_q[1]_carry_eqn;
C1_safe_q[1] = DFFEAS(C1_safe_q[1]_lut_out, GLOBAL(clk), !GLOBAL(start), , , , , , );

--C1L4 is lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|counter_cella1~COUT at LC_X1_Y12_N5
--operation mode is arithmetic

C1L4_cout_0 = !C1L2 # !C1_safe_q[1];
C1L4 = CARRY(C1L4_cout_0);

--C1L5 is lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|counter_cella1~COUTCOUT1_1 at LC_X1_Y12_N5
--operation mode is arithmetic

C1L5_cout_1 = !C1L2 # !C1_safe_q[1];
C1L5 = CARRY(C1L5_cout_1);


--C1_safe_q[0] is lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|safe_q[0] at LC_X1_Y12_N4
--operation mode is arithmetic

C1_safe_q[0]_lut_out = !C1_safe_q[0];
C1_safe_q[0] = DFFEAS(C1_safe_q[0]_lut_out, GLOBAL(clk), !GLOBAL(start), , , , , , );

--C1L2 is lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|counter_cella0~COUT at LC_X1_Y12_N4
--operation mode is arithmetic

C1L2 = CARRY(C1_safe_q[0]);


--A1L4 is clkc1not$en_or~52 at LC_X1_Y11_N7
--operation mode is normal

A1L4 = !C1_safe_q[7] & !C1_safe_q[6] & !C1_safe_q[8] & !C1_safe_q[11];


--A1L5 is clkc1not$en_or~53 at LC_X1_Y12_N0
--operation mode is normal

A1L5 = !C1_safe_q[5] & !C1_safe_q[4] & !C1_safe_q[3] & !C1_safe_q[2];


--A1L04 is reduce_nor~25 at LC_X1_Y12_N2
--operation mode is normal

A1L04 = !C1_safe_q[1] & A1L4 & A1L5;


--A1L6 is clkc1not$en_or~54 at LC_X1_Y11_N8
--operation mode is normal

A1L6 = !C1_safe_q[10] & !C1_safe_q[9];


--clkc1not is clkc1not at LC_X1_Y11_N9
--operation mode is normal

clkc1not = A1L6 & A1L04 & !C1_safe_q[0] # !A1L04 & clkc1not # !A1L6 & clkc1not;


--A1L01 is clkc2not$en_or~10 at LC_X1_Y10_N5
--operation mode is normal

A1L01 = C1_safe_q[9] & A1L04 & C1_safe_q[0];


--A1L93 is reduce_nor~0 at LC_X1_Y11_N6
--operation mode is normal

A1L93 = C1_safe_q[0] # C1_safe_q[9] # C1_safe_q[10] # !A1L04;


--clkc2not is clkc2not at LC_X1_Y10_N3
--operation mode is normal

clkc2not = clkc2not & C1_safe_q[10] # !A1L01 # !A1L93;


--A1L31 is clkc3not$en_or~10 at LC_X1_Y10_N6
--operation mode is normal

A1L31 = C1_safe_q[10] & !C1_safe_q[9];


--A1L7 is clkc1not$en_or~55 at LC_X1_Y12_N1
--operation mode is normal

A1L7 = A1L4 & !C1_safe_q[1] & C1_safe_q[0] & A1L5;


--clkc3not is clkc3not at LC_X1_Y10_N7
--operation mode is normal

clkc3not = clkc3not & !A1L31 # !A1L7 # !A1L93;


--clkc4not is clkc4not at LC_X1_Y10_N2
--operation mode is normal

clkc4not = clkc4not & !C1_safe_q[10] # !A1L01 # !A1L93;


--A1L81 is clrc1$latch$en_or~18 at LC_X1_Y12_N3
--operation mode is normal

A1L81 = A1L4 & C1_safe_q[1] & !C1_safe_q[0] & A1L5;


--clrc1$latch is clrc1$latch at LC_X1_Y10_N4
--operation mode is normal

clrc1$latch = clrc1$latch & !A1L81 # !A1L6 # !A1L93;


--A1L12 is clrc2$latch$en_or~11 at LC_X1_Y10_N0
--operation mode is normal

A1L12 = C1_safe_q[9] & A1L81;


--clrc2$latch is clrc2$latch at LC_X1_Y10_N9
--operation mode is normal

clrc2$latch = clrc2$latch & C1_safe_q[10] # !A1L12 # !A1L93;


--clrc3$latch is clrc3$latch at LC_X1_Y10_N8
--operation mode is normal

clrc3$latch = clrc3$latch & !A1L31 # !A1L81 # !A1L93;


--clrc4$latch is clrc4$latch at LC_X1_Y10_N1
--operation mode is normal

clrc4$latch = clrc4$latch & !C1_safe_q[10] # !A1L12 # !A1L93;


--clk is clk at PIN_K6
--operation mode is input

clk = INPUT();


--start is start at PIN_K5
--operation mode is input

start = INPUT();


--clkc1 is clkc1 at PIN_N6
--operation mode is output

clkc1 = OUTPUT(!clkc1not);


--clkc2 is clkc2 at PIN_P7
--operation mode is output

clkc2 = OUTPUT(!clkc2not);


--clkc3 is clkc3 at PIN_N3
--operation mode is output

clkc3 = OUTPUT(!clkc3not);


--clkc4 is clkc4 at PIN_P1
--operation mode is output

clkc4 = OUTPUT(!clkc4not);


--clrc1 is clrc1 at PIN_P2
--operation mode is output

clrc1 = OUTPUT(clrc1$latch);


--clrc2 is clrc2 at PIN_P5
--operation mode is output

clrc2 = OUTPUT(clrc2$latch);


--clrc3 is clrc3 at PIN_N7
--operation mode is output

clrc3 = OUTPUT(clrc3$latch);


--clrc4 is clrc4 at PIN_N5
--operation mode is output

clrc4 = OUTPUT(clrc4$latch);


--counterTest[11] is counterTest[11] at PIN_M3
--operation mode is output

counterTest[11] = OUTPUT(C1_safe_q[11]);


--counterTest[10] is counterTest[10] at PIN_N4
--operation mode is output

counterTest[10] = OUTPUT(C1_safe_q[10]);


--counterTest[9] is counterTest[9] at PIN_N2
--operation mode is output

counterTest[9] = OUTPUT(C1_safe_q[9]);


--counterTest[8] is counterTest[8] at PIN_M8
--operation mode is output

counterTest[8] = OUTPUT(C1_safe_q[8]);


--counterTest[7] is counterTest[7] at PIN_M7
--operation mode is output

counterTest[7] = OUTPUT(C1_safe_q[7]);


--counterTest[6] is counterTest[6] at PIN_N1
--operation mode is output

counterTest[6] = OUTPUT(C1_safe_q[6]);


--counterTest[5] is counterTest[5] at PIN_M1
--operation mode is output

counterTest[5] = OUTPUT(C1_safe_q[5]);


--counterTest[4] is counterTest[4] at PIN_M6
--operation mode is output

counterTest[4] = OUTPUT(C1_safe_q[4]);


--counterTest[3] is counterTest[3] at PIN_M5
--operation mode is output

counterTest[3] = OUTPUT(C1_safe_q[3]);


--counterTest[2] is counterTest[2] at PIN_M2
--operation mode is output

counterTest[2] = OUTPUT(C1_safe_q[2]);


--counterTest[1] is counterTest[1] at PIN_L8
--operation mode is output

counterTest[1] = OUTPUT(C1_safe_q[1]);


--counterTest[0] is counterTest[0] at PIN_M4
--operation mode is output

counterTest[0] = OUTPUT(C1_safe_q[0]);