crc.map.eqn

在quartus中用VHDL语言开发的crc校验

-- Copyright (C) 1991-2005 Altera Corporation
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-- without limitation, that your use is for the sole purpose of 
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--counter[0] is counter[0]
--operation mode is arithmetic

counter[0]_lut_out = !counter[0];
counter[0] = DFFEAS(counter[0]_lut_out, clk, !start, , , , , , );

--A1L02 is counter[0]~841
--operation mode is arithmetic

A1L02 = CARRY(counter[0]);


--counter[1] is counter[1]
--operation mode is arithmetic

counter[1]_carry_eqn = A1L02;
counter[1]_lut_out = counter[1] $ (counter[1]_carry_eqn);
counter[1] = DFFEAS(counter[1]_lut_out, clk, !start, , , , , , );

--A1L22 is counter[1]~845
--operation mode is arithmetic

A1L22 = CARRY(!A1L02 # !counter[1]);


--counter[2] is counter[2]
--operation mode is arithmetic

counter[2]_carry_eqn = A1L22;
counter[2]_lut_out = counter[2] $ (!counter[2]_carry_eqn);
counter[2] = DFFEAS(counter[2]_lut_out, clk, !start, , , , , , );

--A1L42 is counter[2]~849
--operation mode is arithmetic

A1L42 = CARRY(counter[2] & (!A1L22));


--counter[3] is counter[3]
--operation mode is arithmetic

counter[3]_carry_eqn = A1L42;
counter[3]_lut_out = counter[3] $ (counter[3]_carry_eqn);
counter[3] = DFFEAS(counter[3]_lut_out, clk, !start, , , , , , );

--A1L62 is counter[3]~853
--operation mode is arithmetic

A1L62 = CARRY(!A1L42 # !counter[3]);


--counter[4] is counter[4]
--operation mode is arithmetic

counter[4]_carry_eqn = A1L62;
counter[4]_lut_out = counter[4] $ (!counter[4]_carry_eqn);
counter[4] = DFFEAS(counter[4]_lut_out, clk, !start, , , , , , );

--A1L82 is counter[4]~857
--operation mode is arithmetic

A1L82 = CARRY(counter[4] & (!A1L62));


--counter[5] is counter[5]
--operation mode is arithmetic

counter[5]_carry_eqn = A1L82;
counter[5]_lut_out = counter[5] $ (counter[5]_carry_eqn);
counter[5] = DFFEAS(counter[5]_lut_out, clk, !start, , , , , , );

--A1L03 is counter[5]~861
--operation mode is arithmetic

A1L03 = CARRY(!A1L82 # !counter[5]);


--counter[6] is counter[6]
--operation mode is arithmetic

counter[6]_carry_eqn = A1L03;
counter[6]_lut_out = counter[6] $ (!counter[6]_carry_eqn);
counter[6] = DFFEAS(counter[6]_lut_out, clk, !start, , , , , , );

--A1L23 is counter[6]~865
--operation mode is arithmetic

A1L23 = CARRY(counter[6] & (!A1L03));


--counter[7] is counter[7]
--operation mode is arithmetic

counter[7]_carry_eqn = A1L23;
counter[7]_lut_out = counter[7] $ (counter[7]_carry_eqn);
counter[7] = DFFEAS(counter[7]_lut_out, clk, !start, , , , , , );

--A1L43 is counter[7]~869
--operation mode is arithmetic

A1L43 = CARRY(!A1L23 # !counter[7]);


--counter[8] is counter[8]
--operation mode is arithmetic

counter[8]_carry_eqn = A1L43;
counter[8]_lut_out = counter[8] $ (!counter[8]_carry_eqn);
counter[8] = DFFEAS(counter[8]_lut_out, clk, !start, , , , , , );

--A1L63 is counter[8]~873
--operation mode is arithmetic

A1L63 = CARRY(counter[8] & (!A1L43));


--counter[9] is counter[9]
--operation mode is arithmetic

counter[9]_carry_eqn = A1L63;
counter[9]_lut_out = counter[9] $ (counter[9]_carry_eqn);
counter[9] = DFFEAS(counter[9]_lut_out, clk, !start, , , , , , );

--A1L83 is counter[9]~877
--operation mode is arithmetic

A1L83 = CARRY(!A1L63 # !counter[9]);


--counter[10] is counter[10]
--operation mode is arithmetic

counter[10]_carry_eqn = A1L83;
counter[10]_lut_out = counter[10] $ (!counter[10]_carry_eqn);
counter[10] = DFFEAS(counter[10]_lut_out, clk, !start, , , , , , );

--A1L04 is counter[10]~881
--operation mode is arithmetic

A1L04 = CARRY(counter[10] & (!A1L83));


--counter[11] is counter[11]
--operation mode is normal

counter[11]_carry_eqn = A1L04;
counter[11]_lut_out = counter[11] $ (counter[11]_carry_eqn);
counter[11] = DFFEAS(counter[11]_lut_out, clk, !start, , , , , , );


--A1L46 is reduce_nor~74
--operation mode is normal

A1L46 = !counter[2] & !counter[3] & !counter[4] & !counter[5];


--A1L56 is reduce_nor~75
--operation mode is normal

A1L56 = !counter[6] & !counter[7] & !counter[8] & !counter[11];


--A1L66 is reduce_nor~76
--operation mode is normal

A1L66 = A1L46 & A1L56 & (!counter[0]);


--A1L55 is reduce_nor~0
--operation mode is normal

A1L55 = counter[1] # counter[9] # counter[10] # !A1L66;


--A1L76 is reduce_nor~77
--operation mode is normal

A1L76 = counter[0] & A1L46 & A1L56 & !counter[1];


--A1L65 is reduce_nor~1
--operation mode is normal

A1L65 = counter[9] # counter[10] # !A1L76;


--clkc1not is clkc1not
--operation mode is normal

clkc1not = A1L65 & (clkc1not # !A1L55);


--A1L75 is reduce_nor~2
--operation mode is normal

A1L75 = counter[10] # !A1L76 # !counter[9];


--clkc2not is clkc2not
--operation mode is normal

clkc2not = A1L75 & (clkc2not # !A1L55);


--A1L85 is reduce_nor~3
--operation mode is normal

A1L85 = counter[9] # !A1L76 # !counter[10];


--clkc3not is clkc3not
--operation mode is normal

clkc3not = A1L85 & (clkc3not # !A1L55);


--A1L95 is reduce_nor~4
--operation mode is normal

A1L95 = !A1L76 # !counter[10] # !counter[9];


--clkc4not is clkc4not
--operation mode is normal

clkc4not = A1L95 & (clkc4not # !A1L55);


--A1L06 is reduce_nor~5
--operation mode is normal

A1L06 = counter[9] # counter[10] # !A1L66 # !counter[1];


--clrc1$latch is clrc1$latch
--operation mode is normal

clrc1$latch = A1L06 & (clrc1$latch # !A1L55);


--A1L16 is reduce_nor~6
--operation mode is normal

A1L16 = counter[10] # !A1L66 # !counter[9] # !counter[1];


--clrc2$latch is clrc2$latch
--operation mode is normal

clrc2$latch = A1L16 & (clrc2$latch # !A1L55);


--A1L26 is reduce_nor~7
--operation mode is normal

A1L26 = counter[9] # !A1L66 # !counter[10] # !counter[1];


--clrc3$latch is clrc3$latch
--operation mode is normal

clrc3$latch = A1L26 & (clrc3$latch # !A1L55);


--A1L36 is reduce_nor~8
--operation mode is normal

A1L36 = !A1L66 # !counter[10] # !counter[9] # !counter[1];


--clrc4$latch is clrc4$latch
--operation mode is normal

clrc4$latch = A1L36 & (clrc4$latch # !A1L55);


--clk is clk
--operation mode is input

clk = INPUT();


--start is start
--operation mode is input

start = INPUT();


--clkc1 is clkc1
--operation mode is output

clkc1 = OUTPUT(!clkc1not);


--clkc2 is clkc2
--operation mode is output

clkc2 = OUTPUT(!clkc2not);


--clkc3 is clkc3
--operation mode is output

clkc3 = OUTPUT(!clkc3not);


--clkc4 is clkc4
--operation mode is output

clkc4 = OUTPUT(!clkc4not);


--clrc1 is clrc1
--operation mode is output

clrc1 = OUTPUT(clrc1$latch);


--clrc2 is clrc2
--operation mode is output

clrc2 = OUTPUT(clrc2$latch);


--clrc3 is clrc3
--operation mode is output

clrc3 = OUTPUT(clrc3$latch);


--clrc4 is clrc4
--operation mode is output

clrc4 = OUTPUT(clrc4$latch);


--counterTest[0] is counterTest[0]
--operation mode is output

counterTest[0] = OUTPUT(counter[0]);


--counterTest[1] is counterTest[1]
--operation mode is output

counterTest[1] = OUTPUT(counter[1]);


--counterTest[2] is counterTest[2]
--operation mode is output

counterTest[2] = OUTPUT(counter[2]);


--counterTest[3] is counterTest[3]
--operation mode is output

counterTest[3] = OUTPUT(counter[3]);


--counterTest[4] is counterTest[4]
--operation mode is output

counterTest[4] = OUTPUT(counter[4]);


--counterTest[5] is counterTest[5]
--operation mode is output

counterTest[5] = OUTPUT(counter[5]);


--counterTest[6] is counterTest[6]
--operation mode is output

counterTest[6] = OUTPUT(counter[6]);


--counterTest[7] is counterTest[7]
--operation mode is output

counterTest[7] = OUTPUT(counter[7]);


--counterTest[8] is counterTest[8]
--operation mode is output

counterTest[8] = OUTPUT(counter[8]);


--counterTest[9] is counterTest[9]
--operation mode is output

counterTest[9] = OUTPUT(counter[9]);


--counterTest[10] is counterTest[10]
--operation mode is output

counterTest[10] = OUTPUT(counter[10]);


--counterTest[11] is counterTest[11]
--operation mode is output

counterTest[11] = OUTPUT(counter[11]);