newclk1.vhd

在quartus中用VHDL语言开发的crc校验

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity newclk1 is
     port(clk:in std_logic;
      clr:in std_logic;
      clkc1_4:out std_logic;
      clrc1_4:out std_logic;
      start:out std_logic;
      
 counterTest:   out integer range 0 to 2051
      );
end newclk1;

architecture rtl of newclk1 is
signal counter:integer range 0 to 2052;
signal clkc1_4not:std_logic;
signal startnot:std_logic;
begin

process(clk,clr)
begin
  if(clr='0') then
    counter<=0;
  elsif(clk'event and clk='1') then
    if(counter=2051) then
       counter<=0;
    else
       counter<=counter+1;
    end if;
  end if;
  if(counter=0) then
    clkc1_4not<='1';
    clrc1_4<='1';
    startnot<='1';
  else
    if(counter=2050) then
       clkc1_4not<='0';
    end if;
    if(counter=2051) then
       clrc1_4<='0';
       startnot<='0';
    end if;
    
  end if;
end process;
counterTest<=counter;
clkc1_4<=not clkc1_4not;
start<=not startnot;
end rtl;