crc.tan.rpt

在quartus中用VHDL语言开发的crc校验

; N/A   ; None         ; 8.090 ns   ; lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|safe_q[9]  ; clkc1           ; clk        ;
; N/A   ; None         ; 7.073 ns   ; lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|safe_q[10] ; counterTest[10] ; clk        ;
; N/A   ; None         ; 7.051 ns   ; lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|safe_q[8]  ; counterTest[8]  ; clk        ;
; N/A   ; None         ; 7.050 ns   ; lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|safe_q[9]  ; counterTest[9]  ; clk        ;
; N/A   ; None         ; 7.044 ns   ; lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|safe_q[5]  ; counterTest[5]  ; clk        ;
; N/A   ; None         ; 7.041 ns   ; lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|safe_q[11] ; counterTest[11] ; clk        ;
; N/A   ; None         ; 6.997 ns   ; lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|safe_q[2]  ; counterTest[2]  ; clk        ;
; N/A   ; None         ; 6.996 ns   ; lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|safe_q[3]  ; counterTest[3]  ; clk        ;
; N/A   ; None         ; 6.992 ns   ; lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|safe_q[1]  ; counterTest[1]  ; clk        ;
; N/A   ; None         ; 6.614 ns   ; lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|safe_q[0]  ; counterTest[0]  ; clk        ;
; N/A   ; None         ; 6.602 ns   ; lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|safe_q[6]  ; counterTest[6]  ; clk        ;
; N/A   ; None         ; 6.601 ns   ; lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|safe_q[4]  ; counterTest[4]  ; clk        ;
; N/A   ; None         ; 6.601 ns   ; lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|safe_q[7]  ; counterTest[7]  ; clk        ;
+-------+--------------+------------+--------------------------------------------------------------+-----------------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Sat May 13 15:18:28 2006
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off crc -c crc --timing_analysis_only
Info: Found combinational loop of 1 nodes
    Info: Node "clrc4$latch"
Info: Found combinational loop of 1 nodes
    Info: Node "clrc3$latch"
Info: Found combinational loop of 1 nodes
    Info: Node "clrc2$latch"
Info: Found combinational loop of 1 nodes
    Info: Node "clrc1$latch"
Info: Found combinational loop of 1 nodes
    Info: Node "clkc4not"
Info: Found combinational loop of 1 nodes
    Info: Node "clkc3not"
Info: Found combinational loop of 1 nodes
    Info: Node "clkc2not"
Info: Found combinational loop of 1 nodes
    Info: Node "clkc1not"
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 275.03 MHz between source register "lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|safe_q[2]" and destination register "lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|safe_q[11]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.503 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y12_N6; Fanout = 5; REG Node = 'lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|safe_q[2]'
            Info: 2: + IC(0.535 ns) + CELL(0.575 ns) = 1.110 ns; Loc. = LC_X1_Y12_N6; Fanout = 2; COMB Node = 'lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|counter_cella2~COUTCOUT1_1'
            Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.190 ns; Loc. = LC_X1_Y12_N7; Fanout = 2; COMB Node = 'lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|counter_cella3~COUTCOUT1_1'
            Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.270 ns; Loc. = LC_X1_Y12_N8; Fanout = 2; COMB Node = 'lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|counter_cella4~COUTCOUT1_1'
            Info: 5: + IC(0.000 ns) + CELL(0.258 ns) = 1.528 ns; Loc. = LC_X1_Y12_N9; Fanout = 6; COMB Node = 'lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|counter_cella5~COUT'
            Info: 6: + IC(0.000 ns) + CELL(0.136 ns) = 1.664 ns; Loc. = LC_X1_Y11_N4; Fanout = 1; COMB Node = 'lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|counter_cella10~COUT'
            Info: 7: + IC(0.000 ns) + CELL(0.839 ns) = 2.503 ns; Loc. = LC_X1_Y11_N5; Fanout = 3; REG Node = 'lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|safe_q[11]'
            Info: Total cell delay = 1.968 ns ( 78.63 % )
            Info: Total interconnect delay = 0.535 ns ( 21.37 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 3.109 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_K6; Fanout = 12; CLK Node = 'clk'
                Info: 2: + IC(0.929 ns) + CELL(0.711 ns) = 3.109 ns; Loc. = LC_X1_Y11_N5; Fanout = 3; REG Node = 'lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|safe_q[11]'
                Info: Total cell delay = 2.180 ns ( 70.12 % )
                Info: Total interconnect delay = 0.929 ns ( 29.88 % )
            Info: - Longest clock path from clock "clk" to source register is 3.109 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_K6; Fanout = 12; CLK Node = 'clk'
                Info: 2: + IC(0.929 ns) + CELL(0.711 ns) = 3.109 ns; Loc. = LC_X1_Y12_N6; Fanout = 5; REG Node = 'lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|safe_q[2]'
                Info: Total cell delay = 2.180 ns ( 70.12 % )
                Info: Total interconnect delay = 0.929 ns ( 29.88 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "clk" to destination pin "clkc4" through register "lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|safe_q[7]" is 13.023 ns
    Info: + Longest clock path from clock "clk" to source register is 3.109 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_K6; Fanout = 12; CLK Node = 'clk'
        Info: 2: + IC(0.929 ns) + CELL(0.711 ns) = 3.109 ns; Loc. = LC_X1_Y11_N1; Fanout = 5; REG Node = 'lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|safe_q[7]'
        Info: Total cell delay = 2.180 ns ( 70.12 % )
        Info: Total interconnect delay = 0.929 ns ( 29.88 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 9.690 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y11_N1; Fanout = 5; REG Node = 'lpm_counter:counter_rtl_0|cntr_tb7:auto_generated|safe_q[7]'
        Info: 2: + IC(0.549 ns) + CELL(0.590 ns) = 1.139 ns; Loc. = LC_X1_Y11_N7; Fanout = 3; COMB Node = 'clkc1not$en_or~52'
        Info: 3: + IC(1.255 ns) + CELL(0.292 ns) = 2.686 ns; Loc. = LC_X1_Y12_N2; Fanout = 4; COMB Node = 'reduce_nor~25'
        Info: 4: + IC(1.254 ns) + CELL(0.114 ns) = 4.054 ns; Loc. = LC_X1_Y11_N6; Fanout = 14; COMB Node = 'reduce_nor~0'
        Info: 5: + IC(0.000 ns) + CELL(1.978 ns) = 6.032 ns; Loc. = LC_X1_Y10_N2; Fanout = 2; COMB LOOP Node = 'clkc4not'
            Info: Loc. = LC_X1_Y10_N2; Node "clkc4not"
        Info: 6: + IC(1.534 ns) + CELL(2.124 ns) = 9.690 ns; Loc. = PIN_P1; Fanout = 0; PIN Node = 'clkc4'
        Info: Total cell delay = 5.098 ns ( 52.61 % )
        Info: Total interconnect delay = 4.592 ns ( 47.39 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sat May 13 15:18:29 2006
    Info: Elapsed time: 00:00:03