led.vhd

vhdl实现“PLD电子技术”（文字显示）

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity disp is port (clk:in std_logic;
                     clka:in std_logic;
							addr:inout std_logic_vector(2 downto 0);
							data:out std_logic_vector(7 downto 0)
							);
end;

architecture disp_arch of disp is
type romtable is array(0 to 7) of std_logic_vector(7 downto 0);

constant roma:romtable:=romtable'(  "10000001",
												"10111101",
												"10111101",
												"10111101",
												"10000001",
												"10111111",
												"10111111",
												"10111111"
											);
constant romb:romtable:=romtable'(  "10111111",
												"10111111",
												"10111111",
												"10111111",
												"10111111",
												"10111111",
												"10111111",
												"10000000"
											);
constant romc:romtable:=romtable'(  "10000001",
												"10111110",
												"10111110",
												"10111110",
												"10111110",
												"10111110",
												"10111110",
												"10000001"
											);
constant romd:romtable:=romtable'(  "11101111",
												"00000001",
												"01101101",
												"00000001",
												"01101101",
												"00000001",
												"11101111",
												"11100001"
											);											
constant rome:romtable:=romtable'(  "00000000",
												"11111101",
												"11111011",
												"00000000",
												"11110111",
												"11110111",
												"11110111",
												"11100111"
											);
constant romf:romtable:=romtable'(  "10111011",
												"10100000",
												"00011011",
												"10100000",
												"10010101",
												"00111011",
												"10110101",
												"00101110"
											);
constant romg:romtable:=romtable'(  "11101011",
												"11101101",
												"00000000",
												"11000111",
												"10101011",
												"01101101",
												"11101111",
												"11101111"
											);
constant romh:romtable:=romtable'(  "11100111",
												"11100111",
												"11100111",
												"11100111",
												"11100111",
												"11100111",
												"11111111",
												"11100111"
											);


signal q:std_logic_vector(5 downto 0);
begin 
  p1:process(clka)
  begin
     if rising_edge(clka) then
	   q<=q+'1';
	end if;
  end process p1;
  
  p2:process(clk)
  begin 
   if rising_edge(clk) then 
     addr<=addr+'1';
  	end if; 
  end process p2;
 
 p3:process(addr)
 variable a:integer range 0 to 127;
 variable addr1:integer range 0 to 15;
 begin
  a:=conv_integer(q);
  addr1:=conv_integer(addr);
  case a is
    when 0 to 7   => data<=roma(addr1);
    when 8 to 15  => data<=romb(addr1);							
    when 16 to 23 => data<=romc(addr1);
    when 24 to 31 => data<=romd(addr1);	
    when 32 to 39 => data<=rome(addr1); 
    when 40 to 47 => data<=romf(addr1);
    when 48 to 55 => data<=romg(addr1);
	 when others   => data<=romh(addr1);
  end case;
 end process;
end;