elock.vhd

电子锁的vhdl实现 （pld数字系统设计上）

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity elock is port(clk,k1,k2,k3,k4,k5,k6,k7,k8,k9,k10:in std_logic;
                      row:out std_logic_vector(2 downto 0);
                      led:out std_logic_vector(7 downto 0));
end elock;


architecture behavioral of elock is
signal count:std_logic_vector(1 downto 0);
signal count1:std_logic_vector(3 downto 0);
type states is (s4,s3,s2,s1,s0);
signal state:states:=s0;
signal next_state:states:=s0;
signal en,carry,op,k11,k22,k33,k44,k55,k66,k77,k88,k99,k100:std_logic;
signal row1:std_logic_vector(2 downto 0);

begin 
   p1:process(clk)
	   begin
		   if rising_edge(clk) then
			  count<=count+'1';
			end if;
	end process p1;

   p2:process(clk)
	   begin
		   if rising_edge(clk) then
			 if count="11" then 
			   carry<='1';
			 else
			   carry<='0';
			 end if;
			end if;
	end process p2;

   p3:process(carry,k1,k2,k3,k6,k9)
      begin
		  if rising_edge(carry) then
		      if(k1='0') then
				   k11<='0';
				else 
				   k11<='1';
			   end if;
				
		      if(k2='0') then
				   k22<='0';
				else 
				   k22<='1';
			   end if;
				
		      if(k3='0') then
				   k33<='0';
				else 
				   k33<='1';
			   end if;
				
		      if(k4='0') then
				   k44<='0';
				else 
				   k44<='1';
			   end if;
				
		      if(k5='0') then
				   k11<='0';
				else 
				   k55<='1';
			   end if;
				
		      if(k6='0') then
				   k66<='0';
				else 
				   k66<='1';
			   end if;
				
		      if(k7='0') then
				   k77<='0';
				else 
				   k77<='1';
			   end if;
				
		      if(k8='0') then
				   k88<='0';
				else 
				   k88<='1';
			   end if;
				
		      if(k9='0') then
				   k99<='0';
				else 
				   k99<='1';
			   end if;
				
		      if(k10='0') then
				   k100<='0';
				else 
				   k100<='1';
			   end if;
		  end if;
	 end process p3;
	 
	 p4:process(carry)
	    begin 
		  if rising_edge(carry) then 
		    state<=next_state;
		end if;
	 end process p4;
	 
	 p5:process(state,k11,k22,k33,k44,k55,k66,k77,k88,k99,k100)
	    begin
		   case state is
			  when s0=>if(k33='0' and en='1') then 
			             next_state<=s1;
							 op<='0';
						  else
							  next_state<=s0;
					     end if;
			  when s1=>if(k22='0' and en='1') then 
			             next_state<=s2;
					       op<='0';
						  else
							 next_state<=s1;
						  end if;	 
			  when s2=>if(k11='0' and en='1') then 
			             next_state<=s3;
					       op<='0';
						  else
							 next_state<=s2;
						  end if;
			  when s3=>if(k66='0' and en='1') then 
			             next_state<=s4;
			 		       op<='0';
						  else
							 next_state<=s3;
						  end if;
		     when s4=>op<='1'; 
						  next_state<=s0;
						  
			  when others=>next_state<=s0;
			end case;
			
			if k100='0' then next_state<=s0;
			end if;
	 end process p5;
	 
	 
	p6:process(carry,k11,k22,k33,k44,k55,k66,k77,k88,k99,k100)
	   begin
		  if rising_edge(carry) then
		     if k100='0' then 
			     count1<="0000";
			  elsif op='1' then 
			     count1<="1111";
			  elsif(en='0' and op='0') then 
			     count1<="1110";
			  elsif(en='0' and (k11='0' or k22='0' or k33='0' or k44='0' or k55='0' or k66='0' or k77='0' or k88='0' or k99='0'))then
			     count1<=count1+1;
           end if;
	      end if;	 	 
	 end process p6;
	 
	p7:process(count1)
	   begin 
		   if count1<="011" then 
			    en<='1';
		   else
			    en<='0';
			end if;
   end process p7;
	
	
	with count1 select
	 led<="01100000"  when  "0001",
         "11011010"  when  "0010",
	      "11110010"  when  "0011",
         "01100110"  when  "0100",
	      "10110110"  when  "0101",
         "10111110"  when  "0110",
	      "11100000"  when  "0111",
			"11111110"  when  "1000",
			"11110110"  when  "1001",
			"01101110"  when  "1111",
			"10011110"  when  "1110",
			"11111100"  when  OTHERS;
	
	row<="101";

end behavioral;