fir.vhd

滤波器的vhdl实现 滤波器的vhdl实现

library lpm;
use lpm.lpm_components.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity fir is 
          generic(w1:integer:=9;
                  w2:integer:=18;
						w3:integer:=19;
						w4:integer:=11;
						 L:integer:=4;
					mpipe:integer:=3
					  );
			
			 port(   clk:in std_logic;
			      load_x:in std_logic;
					  x_in:in std_logic_vector(w1-1 downto 0);
					  c_in:in std_logic_vector(w1-1 downto 0);
					 y_out:out std_logic_vector(w4-1 downto 0)
					);
end;

architecture behave of fir is 
subtype n1bit is std_logic_vector(w1-1 downto 0);
subtype n2bit is std_logic_vector(w2-1 downto 0);
subtype n3bit is std_logic_vector(w3-1 downto 0);
type array_n1bit is array(0 to L-1) of n1bit;
type array_n2bit is array(0 to L-1) of n2bit;
type array_n3bit is array(0 to L-1) of n3bit;

signal x:n1bit;
signal y:n3bit;
signal c:array_n1bit;
signal p:array_n2bit;
signal a:array_n3bit;

begin 
  load:process
  begin 
    wait until clk='1';
	 if(load_x='0') then
	    c(L-1)<=c_in;
		 for i in L-2 downto 0 loop
		 c(i)<=c(i+1);
		 end loop;
	  else
	    x<=x_in;
	  end if;
   end process load;
	
	sop:process(clk)
	begin 
	  if clk'event and (clk='1') then
	     for i in 0 to L-2 loop
		   a(i)<=(p(i)(w2-1)&p(i))+a(i+1);
		  end loop;
        a(L-1)<=p(L-1)(w2-1)&p(L-1);
		  end if;
		  y<=a(0);
	end process sop;
	
	MulGen:for i in 0 to L-1 generate
	Muls:lpm_mult
	       generic map(lpm_widtha=>w1,lpm_widthb=>w1,lpm_pipeline=>mpipe,
			           lpm_representation=>"SIGNED",lpm_widthp=>w2,lpm_widths=>w2)
			 port map(clock=>clk,dataa=>x,datab=>c(i),result=>p(i));
	 end generate;
	 
	 y_out<=y(w3-1 downto w3-w4);
end;