statectrl.v

Verilog实现的CPU程序

  module cpu_sctrl(load_acc,mem_r,mem_w,inc_pc,load_pc,load_ir,halt,opcode,fetch,zero,clk,clk2,reset);

   output load_acc,mem_r,mem_w,inc_pc,load_pc,load_ir,halt;
   reg load_acc,mem_r,mem_w,inc_pc,load_pc,load_ir,halt;
   input[2:0] opcode;
   input fetch,zero,clk,clk2,reset;
   parameter Hlt=3'b000,Skz=3'b001,Add=3'b010,And=3'b011,Xor=3'b100,Lda=3'b101,Sto=3'b110,Jmp=3'b111;
   always @(posedge fetch)
         if(reset)//
             ctl_state;//
   always @(negedge reset)
            begin
              disable ctl_state;
             {inc_pc,load_acc,load_pc,mem_w,mem_r,load_ir,halt}=7'b0;

            end
   always @( posedge reset)
            @(posedge fetch) ctl_state;
        task ctl_state;
              begin
                {inc_pc,load_acc,load_pc,mem_w,mem_r,load_ir,halt}=7'b0000000;
       
              @(posedge clk)
                   {inc_pc,load_acc,load_pc,mem_w,mem_r,load_ir,halt}=7'b0000100;
              @(negedge clk)
                  {inc_pc,load_acc,load_pc,mem_w,mem_r,load_ir,halt}=7'b0000110;
              @(posedge clk)
                  {inc_pc,load_acc,load_pc,mem_w,mem_r,load_ir,halt}=7'b0000110;
              @(negedge clk)
                  if(opcode==Hlt)
                  {inc_pc,load_acc,load_pc,mem_w,mem_r,load_ir,halt}=7'b1000001;
                  else
                  {inc_pc,load_acc,load_pc,mem_w,mem_r,load_ir,halt}=7'b1000000;
              @(posedge clk)
                  if((opcode==Add)||(opcode==And)||(opcode==Xor)||(opcode==Lda))
                  {inc_pc,load_acc,load_pc,mem_w,mem_r,load_ir,halt}=7'b1000100;
                  else
                  {inc_pc,load_acc,load_pc,mem_w,mem_r,load_ir,halt}=7'b0000000;
              @(negedge clk)
                  if(opcode==Jmp)
                  {inc_pc,load_acc,load_pc,mem_w,mem_r,load_ir,halt}=7'b0010000;
                  else if((opcode==Skz)&&zero)
                  {inc_pc,load_acc,load_pc,mem_w,mem_r,load_ir,halt}=7'b1000000;    
                  else if((opcode==Add)||(opcode==And)||(opcode==Xor)||(opcode==Lda))
                  {inc_pc,load_acc,load_pc,mem_w,mem_r,load_ir,halt}=7'b0100100;
                  else
                  {inc_pc,load_acc,load_pc,mem_r,load_ir,halt}=7'b0000000;    
              @(posedge clk)
                  if(opcode==Jmp)
                  {inc_pc,load_acc,load_pc,mem_w,mem_r,load_ir,halt}=7'b1010000;
                  else if(opcode==Sto)
                  {inc_pc,load_acc,load_pc,mem_w,mem_r,load_ir,halt}=7'b0001000;
                  else if((opcode==Skz)&&zero)
                  {inc_pc,load_acc,load_pc,mem_w,mem_r,load_ir,halt}=7'b1000000;

                  else if((opcode==Add)||(opcode==And)||(opcode==Xor)||(opcode==Lda))
                  {inc_pc,load_acc,load_pc,mem_w,mem_r,load_ir,halt}=7'b0100100;
                  else
                  {inc_pc,load_acc,load_pc,mem_w,mem_r,load_ir,halt}=7'b0000000;
       end  
         endtask
 endmodule