cpu_register.v

Verilog实现的CPU程序

module cpu_register(data_out,clk,reset,en,data_in);
 output[7:0] data_out;
 input[7:0] data_in;
 input clk,reset,en;
 reg[7:0] data_out;
 always@( posedge clk or negedge reset)
   if(!reset)
      data_out=8'b0;//<=
      else if(en)
             data_out=data_in;//else
  endmodule