uart_51_tb.v

符合8051协议规范的UART的Verilog源代码.该压缩包是一个modelsim的工程.

module uart_51_tb;
reg clk,rst;
reg [3:0] osc_cnt;
reg [7:0] addr1,addr2;
reg wr;
reg wr_bit;
reg [7:0] TH1,TL1;
reg [7:0] DIN;
reg t1_ow;
wire intr;
parameter clk_period=6;
always                                      //clk gen
   #(clk_period/2)  clk=~clk;
   
initial                                     //rst_gen
begin
clk=1'b0;
rst=0;
#(3*clk_period)rst=1'b1;
#(3*clk_period)rst=1'b0;

#(3*clk_period);                            //write sbuf
wr=1'b1;
wr_bit=1'b0;
addr1=8'h99;
DIN=8'b0101_1010;
#(3*clk_period);
wr=1'b0;

//#(15000*clk_period);
//begin
//#(3*clk_period);                            //write sbuf
//wr=1'b1;
//wr_bit=1'b0;
//addr1=8'h99;
//DIN=8'b1111_0000;
//#(3*clk_period);
//wr=1'b0;
//end

//#(3*clk_period);                            //write scon
//wr=1'b1;
//wr_bit=1'b0;
//addr1=8'h98;
//DIN=8'b0101_0000;
//#(3*clk_period);
//wr=1'b0;




#(20000*clk_period);
$stop;
end

always @(posedge clk or posedge rst)   //osc_cnt output
if(rst)
osc_cnt<=4'b0000;
else if(osc_cnt==4'b1011)
osc_cnt<=4'b0000;
else
osc_cnt<=osc_cnt+1'b1;


always @(posedge clk or posedge rst)
if(rst)
{TH1,TL1}<=16'hFFFD;
else if(osc_cnt==4'b1011)
     if({TH1,TL1}==16'hFFFF)
     {TH1,TL1}<=16'hFFFD;
     else
     {TH1,TL1}<={TH1,TL1}+1'b1;
     
always @(posedge clk or posedge rst)
if(rst)
begin
t1_ow<=1'b0;
end
else if(t1_ow==1'b1)
t1_ow<=1'b0;
else if(TH1==8'b1111_1111&&TL1==8'b1111_1111&&osc_cnt==4'b1010)
t1_ow<=1'b1;

uart_51 u1_uart_51(.clk(clk),
		  .rst(rst),
		  .wr(wr),
		  .wr_bit(),
		  .addr(addr1),
		  .bit_in(),
		  .data_in(DIN),
		  .t1_ow(t1_ow),
		  .rxd(),
		  .txd(txd),
		  .intr(),
		  .data_out(),
		  .scon(),
		  .pcon(),
		  .rx_sbuf());
uart_51 u2_uart_51(.clk(clk),
		  .rst(rst),
		  .wr(wr),
		  .wr_bit(1'b0),
		  .addr(addr2),
		  .bit_in(),
		  .data_in(DIN),
		  .t1_ow(t1_ow),
		  .rxd(txd),
		  .txd(),
		  .intr(intr),
		  .data_out(),
		  .scon(),
		  .pcon(),
		  .rx_sbuf());
integer fp;		  
initial
begin
     fp = $fopen ("sim_result.txt");
end 
always @ (posedge clk)		  	
$fdisplay(fp,"%b",{wr,addr1,DIN});	  
endmodule