aqusition.vhd

来自「此程序用于视频采集过程中CPLD对时序的转换与组合代码」· VHDL 代码 · 共 75 行

library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity acquistion is 
port
(
vcc,clkx1,jumper,reset,vref,href,llc2: in std_logic;
outer: out std_logic
);
end acquistion;
architecture structure of acquistion is
signal sig_save1: std_logic;
signal sig_save2: std_logic;
signal q1,q2,s1,s2,divclk1,divclk2,a1,a2,start: std_logic;
signal counter1:std_logic_vector(4 downto 0):="00000";
signal counter2:std_logic_vector(4 downto 0):="00000";
signal tempdivclk1:std_logic:='0';
signal tempdivclk2:std_logic:='0';
begin
start<=clkx1 or jumper;
process(start,vcc,s1)
begin

s2<=not reset;
s1<=not(s2 or q2); 

--*/D???1/*--
if(s1='1')then
   sig_save1<='0';
   elsif(tclk0'event and tclk0='1')then
   sig_save1<=vcc;
end if;
q1<=sig_save1;
end process;

--*/D???2/*--
process(q1,vref,s2)
begin
if(s2='1')then

   sig_save2<='0';
   elsif(vref'event and vref='1')then
sig_save2<=q1;
end if;
q2<=sig_save2;
end process;

--*/href???/*--
process(href)
begin
if(href'event and href='1')then

    tempdivclk1<=not tempdivclk1;
 end if;

divclk1<=tempdivclk1;
end process;

--* c2???/*--
process(llc2)
begin
if(llc2'event and llc2='1')then

    tempdivclk2<=not tempdivclk2;
 end if;

divclk2<=tempdivclk2;
end process;

a1<=href and divclk1;
a2<=llc2 and divclk2;

outer<=q2 and a1 and a2;
end structure;