📄 dzy.tan.rpt
字号:
; N/A ; None ; 5.621 ns ; DIN[0] ; STATE.s2 ; CLK ;
; N/A ; None ; 5.493 ns ; COMM ; STATE.s0 ; CLK ;
; N/A ; None ; 5.271 ns ; COMM ; ERROR1~reg0 ; CLK ;
; N/A ; None ; 5.263 ns ; COMM ; COMMODITY2~reg0 ; CLK ;
; N/A ; None ; 5.241 ns ; DIN[1] ; STATE.s1 ; CLK ;
; N/A ; None ; 5.203 ns ; COMM ; GIVE_CHANGE2~reg0 ; CLK ;
; N/A ; None ; 4.728 ns ; DIN[0] ; STATE.s1 ; CLK ;
; N/A ; None ; 4.715 ns ; COMM ; STATE.s3 ; CLK ;
; N/A ; None ; 4.199 ns ; COMM ; ERROR2~reg0 ; CLK ;
; N/A ; None ; 1.509 ns ; RST ; COMMODITY1~reg0 ; CLK ;
; N/A ; None ; 1.509 ns ; RST ; GIVE_CHANGE1~reg0 ; CLK ;
; N/A ; None ; 0.807 ns ; RST ; ERROR1~reg0 ; CLK ;
; N/A ; None ; 0.807 ns ; RST ; COMMODITY2~reg0 ; CLK ;
; N/A ; None ; 0.771 ns ; RST ; GIVE_CHANGE2~reg0 ; CLK ;
; N/A ; None ; 0.771 ns ; RST ; ERROR2~reg0 ; CLK ;
+-------+--------------+------------+--------+-------------------+----------+
+-----------------------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+-------------------+--------------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+-------------------+--------------+------------+
; N/A ; None ; 7.609 ns ; COMMODITY1~reg0 ; COMMODITY1 ; CLK ;
; N/A ; None ; 7.272 ns ; ERROR1~reg0 ; ERROR1 ; CLK ;
; N/A ; None ; 7.108 ns ; COMMODITY2~reg0 ; COMMODITY2 ; CLK ;
; N/A ; None ; 6.415 ns ; GIVE_CHANGE2~reg0 ; GIVE_CHANGE2 ; CLK ;
; N/A ; None ; 6.411 ns ; GIVE_CHANGE1~reg0 ; GIVE_CHANGE1 ; CLK ;
; N/A ; None ; 6.411 ns ; ERROR2~reg0 ; ERROR2 ; CLK ;
+-------+--------------+------------+-------------------+--------------+------------+
+---------------------------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+--------+-------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+--------+-------------------+----------+
; N/A ; None ; -0.719 ns ; RST ; GIVE_CHANGE2~reg0 ; CLK ;
; N/A ; None ; -0.719 ns ; RST ; ERROR2~reg0 ; CLK ;
; N/A ; None ; -0.755 ns ; RST ; ERROR1~reg0 ; CLK ;
; N/A ; None ; -0.755 ns ; RST ; COMMODITY2~reg0 ; CLK ;
; N/A ; None ; -1.457 ns ; RST ; COMMODITY1~reg0 ; CLK ;
; N/A ; None ; -1.457 ns ; RST ; GIVE_CHANGE1~reg0 ; CLK ;
; N/A ; None ; -4.147 ns ; COMM ; ERROR2~reg0 ; CLK ;
; N/A ; None ; -4.218 ns ; COMM ; COMMODITY1~reg0 ; CLK ;
; N/A ; None ; -4.224 ns ; COMM ; GIVE_CHANGE1~reg0 ; CLK ;
; N/A ; None ; -4.454 ns ; COMM ; COMMODITY2~reg0 ; CLK ;
; N/A ; None ; -4.455 ns ; COMM ; ERROR1~reg0 ; CLK ;
; N/A ; None ; -4.656 ns ; COMM ; STATE.s0 ; CLK ;
; N/A ; None ; -4.663 ns ; COMM ; STATE.s3 ; CLK ;
; N/A ; None ; -4.676 ns ; DIN[0] ; STATE.s1 ; CLK ;
; N/A ; None ; -4.682 ns ; DIN[0] ; STATE.s2 ; CLK ;
; N/A ; None ; -4.684 ns ; DIN[0] ; GIVE_CHANGE1~reg0 ; CLK ;
; N/A ; None ; -5.139 ns ; DIN[1] ; STATE.s2 ; CLK ;
; N/A ; None ; -5.151 ns ; COMM ; GIVE_CHANGE2~reg0 ; CLK ;
; N/A ; None ; -5.183 ns ; DIN[1] ; GIVE_CHANGE2~reg0 ; CLK ;
; N/A ; None ; -5.189 ns ; DIN[1] ; STATE.s1 ; CLK ;
; N/A ; None ; -5.338 ns ; DIN[0] ; GIVE_CHANGE2~reg0 ; CLK ;
; N/A ; None ; -5.681 ns ; DIN[0] ; STATE.s3 ; CLK ;
; N/A ; None ; -5.718 ns ; DIN[0] ; COMMODITY2~reg0 ; CLK ;
; N/A ; None ; -5.842 ns ; DIN[1] ; STATE.s0 ; CLK ;
; N/A ; None ; -5.885 ns ; DIN[0] ; STATE.s0 ; CLK ;
; N/A ; None ; -5.905 ns ; DIN[1] ; STATE.s3 ; CLK ;
; N/A ; None ; -5.972 ns ; DIN[0] ; ERROR1~reg0 ; CLK ;
; N/A ; None ; -6.110 ns ; DIN[1] ; COMMODITY2~reg0 ; CLK ;
; N/A ; None ; -6.115 ns ; DIN[0] ; ERROR2~reg0 ; CLK ;
; N/A ; None ; -6.340 ns ; DIN[1] ; ERROR2~reg0 ; CLK ;
; N/A ; None ; -6.407 ns ; DIN[1] ; ERROR1~reg0 ; CLK ;
; N/A ; None ; -6.653 ns ; DIN[0] ; COMMODITY1~reg0 ; CLK ;
; N/A ; None ; -6.809 ns ; DIN[1] ; COMMODITY1~reg0 ; CLK ;
; N/A ; None ; -6.809 ns ; DIN[1] ; GIVE_CHANGE1~reg0 ; CLK ;
+---------------+-------------+-----------+--------+-------------------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
Info: Processing started: Fri Dec 28 11:12:47 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off DZY -c DZY --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" Internal fmax is restricted to 275.03 MHz between source register "STATE.s0" and destination register "COMMODITY1~reg0"
Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 3.052 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y2_N0; Fanout = 10; REG Node = 'STATE.s0'
Info: 2: + IC(0.580 ns) + CELL(0.114 ns) = 0.694 ns; Loc. = LC_X10_Y2_N2; Fanout = 3; COMB Node = 'COMMODITY1~537'
Info: 3: + IC(0.438 ns) + CELL(0.292 ns) = 1.424 ns; Loc. = LC_X10_Y2_N7; Fanout = 1; COMB Node = 'COMMODITY1~540'
Info: 4: + IC(0.182 ns) + CELL(0.114 ns) = 1.720 ns; Loc. = LC_X10_Y2_N8; Fanout = 2; COMB Node = 'COMMODITY1~541'
Info: 5: + IC(0.465 ns) + CELL(0.867 ns) = 3.052 ns; Loc. = LC_X10_Y2_N1; Fanout = 1; REG Node = 'COMMODITY1~reg0'
Info: Total cell delay = 1.387 ns ( 45.45 % )
Info: Total interconnect delay = 1.665 ns ( 54.55 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "CLK" to destination register is 2.733 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 10; CLK Node = 'CLK'
Info: 2: + IC(0.553 ns) + CELL(0.711 ns) = 2.733 ns; Loc. = LC_X10_Y2_N1; Fanout = 1; REG Node = 'COMMODITY1~reg0'
Info: Total cell delay = 2.180 ns ( 79.77 % )
Info: Total interconnect delay = 0.553 ns ( 20.23 % )
Info: - Longest clock path from clock "CLK" to source register is 2.733 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 10; CLK Node = 'CLK'
Info: 2: + IC(0.553 ns) + CELL(0.711 ns) = 2.733 ns; Loc. = LC_X10_Y2_N0; Fanout = 10; REG Node = 'STATE.s0'
Info: Total cell delay = 2.180 ns ( 79.77 % )
Info: Total interconnect delay = 0.553 ns ( 20.23 % )
Info: + Micro clock to output delay of source is 0.224 ns
Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "COMMODITY1~reg0" (data pin = "DIN[1]", clock pin = "CLK") is 7.706 ns
Info: + Longest pin to register delay is 10.402 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_34; Fanout = 17; PIN Node = 'DIN[1]'
Info: 2: + IC(5.300 ns) + CELL(0.442 ns) = 7.211 ns; Loc. = LC_X8_Y2_N4; Fanout = 3; COMB Node = 'Selector9~13'
Info: 3: + IC(1.121 ns) + CELL(0.442 ns) = 8.774 ns; Loc. = LC_X10_Y2_N7; Fanout = 1; COMB Node = 'COMMODITY1~540'
Info: 4: + IC(0.182 ns) + CELL(0.114 ns) = 9.070 ns; Loc. = LC_X10_Y2_N8; Fanout = 2; COMB Node = 'COMMODITY1~541'
Info: 5: + IC(0.465 ns) + CELL(0.867 ns) = 10.402 ns; Loc. = LC_X10_Y2_N1; Fanout = 1; REG Node = 'COMMODITY1~reg0'
Info: Total cell delay = 3.334 ns ( 32.05 % )
Info: Total interconnect delay = 7.068 ns ( 67.95 % )
Info: + Micro setup delay of destination is 0.037 ns
Info: - Shortest clock path from clock "CLK" to destination register is 2.733 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 10; CLK Node = 'CLK'
Info: 2: + IC(0.553 ns) + CELL(0.711 ns) = 2.733 ns; Loc. = LC_X10_Y2_N1; Fanout = 1; REG Node = 'COMMODITY1~reg0'
Info: Total cell delay = 2.180 ns ( 79.77 % )
Info: Total interconnect delay = 0.553 ns ( 20.23 % )
Info: tco from clock "CLK" to destination pin "COMMODITY1" through register "COMMODITY1~reg0" is 7.609 ns
Info: + Longest clock path from clock "CLK" to source register is 2.733 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 10; CLK Node = 'CLK'
Info: 2: + IC(0.553 ns) + CELL(0.711 ns) = 2.733 ns; Loc. = LC_X10_Y2_N1; Fanout = 1; REG Node = 'COMMODITY1~reg0'
Info: Total cell delay = 2.180 ns ( 79.77 % )
Info: Total interconnect delay = 0.553 ns ( 20.23 % )
Info: + Micro clock to output delay of source is 0.224 ns
Info: + Longest register to pin delay is 4.652 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y2_N1; Fanout = 1; REG Node = 'COMMODITY1~reg0'
Info: 2: + IC(2.528 ns) + CELL(2.124 ns) = 4.652 ns; Loc. = PIN_31; Fanout = 0; PIN Node = 'COMMODITY1'
Info: Total cell delay = 2.124 ns ( 45.66 % )
Info: Total interconnect delay = 2.528 ns ( 54.34 % )
Info: th for register "GIVE_CHANGE2~reg0" (data pin = "RST", clock pin = "CLK") is -0.719 ns
Info: + Longest clock path from clock "CLK" to destination register is 2.733 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 10; CLK Node = 'CLK'
Info: 2: + IC(0.553 ns) + CELL(0.711 ns) = 2.733 ns; Loc. = LC_X11_Y2_N4; Fanout = 3; REG Node = 'GIVE_CHANGE2~reg0'
Info: Total cell delay = 2.180 ns ( 79.77 % )
Info: Total interconnect delay = 0.553 ns ( 20.23 % )
Info: + Micro hold delay of destination is 0.015 ns
Info: - Shortest pin to register delay is 3.467 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 9; PIN Node = 'RST'
Info: 2: + IC(1.131 ns) + CELL(0.867 ns) = 3.467 ns; Loc. = LC_X11_Y2_N4; Fanout = 3; REG Node = 'GIVE_CHANGE2~reg0'
Info: Total cell delay = 2.336 ns ( 67.38 % )
Info: Total interconnect delay = 1.131 ns ( 32.62 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
Info: Allocated 106 megabytes of memory during processing
Info: Processing ended: Fri Dec 28 11:12:49 2007
Info: Elapsed time: 00:00:02
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