📄 dzy.tan.rpt
字号:
Classic Timing Analyzer report for DZY
Fri Dec 28 11:12:48 2007
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'CLK'
6. tsu
7. tco
8. th
9. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+-----------------+-------------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+-----------------+-------------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 7.706 ns ; DIN[1] ; GIVE_CHANGE1~reg0 ; -- ; CLK ; 0 ;
; Worst-case tco ; N/A ; None ; 7.609 ns ; COMMODITY1~reg0 ; COMMODITY1 ; CLK ; -- ; 0 ;
; Worst-case th ; N/A ; None ; -0.719 ns ; RST ; ERROR2~reg0 ; -- ; CLK ; 0 ;
; Clock Setup: 'CLK' ; N/A ; None ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.s0 ; GIVE_CHANGE1~reg0 ; CLK ; CLK ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+-----------------+-------------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C3T144C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK' ;
+-------+------------------------------------------------+-------------------+-------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-------------------+-------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.s0 ; COMMODITY1~reg0 ; CLK ; CLK ; None ; None ; 3.052 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.s0 ; GIVE_CHANGE1~reg0 ; CLK ; CLK ; None ; None ; 3.052 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.s1 ; COMMODITY1~reg0 ; CLK ; CLK ; None ; None ; 2.973 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.s1 ; GIVE_CHANGE1~reg0 ; CLK ; CLK ; None ; None ; 2.973 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.s2 ; COMMODITY2~reg0 ; CLK ; CLK ; None ; None ; 2.782 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.s2 ; STATE.s0 ; CLK ; CLK ; None ; None ; 2.767 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.s3 ; COMMODITY1~reg0 ; CLK ; CLK ; None ; None ; 2.765 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.s3 ; GIVE_CHANGE1~reg0 ; CLK ; CLK ; None ; None ; 2.765 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.s1 ; STATE.s0 ; CLK ; CLK ; None ; None ; 2.724 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.s3 ; COMMODITY2~reg0 ; CLK ; CLK ; None ; None ; 2.708 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.s3 ; ERROR1~reg0 ; CLK ; CLK ; None ; None ; 2.692 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.s0 ; COMMODITY2~reg0 ; CLK ; CLK ; None ; None ; 2.649 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.s2 ; STATE.s3 ; CLK ; CLK ; None ; None ; 2.636 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.s2 ; COMMODITY1~reg0 ; CLK ; CLK ; None ; None ; 2.601 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.s2 ; GIVE_CHANGE1~reg0 ; CLK ; CLK ; None ; None ; 2.601 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.s3 ; STATE.s0 ; CLK ; CLK ; None ; None ; 2.598 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.s0 ; ERROR1~reg0 ; CLK ; CLK ; None ; None ; 2.540 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.s0 ; STATE.s0 ; CLK ; CLK ; None ; None ; 2.516 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.s3 ; STATE.s3 ; CLK ; CLK ; None ; None ; 2.465 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.s1 ; COMMODITY2~reg0 ; CLK ; CLK ; None ; None ; 2.454 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.s1 ; STATE.s2 ; CLK ; CLK ; None ; None ; 2.399 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.s2 ; STATE.s2 ; CLK ; CLK ; None ; None ; 2.392 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.s2 ; ERROR1~reg0 ; CLK ; CLK ; None ; None ; 2.358 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.s1 ; ERROR1~reg0 ; CLK ; CLK ; None ; None ; 2.030 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.s1 ; STATE.s3 ; CLK ; CLK ; None ; None ; 1.777 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; ERROR1~reg0 ; ERROR1~reg0 ; CLK ; CLK ; None ; None ; 1.767 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.s0 ; GIVE_CHANGE2~reg0 ; CLK ; CLK ; None ; None ; 1.761 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.s3 ; GIVE_CHANGE2~reg0 ; CLK ; CLK ; None ; None ; 1.699 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; GIVE_CHANGE2~reg0 ; GIVE_CHANGE2~reg0 ; CLK ; CLK ; None ; None ; 1.693 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.s0 ; STATE.s1 ; CLK ; CLK ; None ; None ; 1.497 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.s0 ; ERROR2~reg0 ; CLK ; CLK ; None ; None ; 1.388 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; COMMODITY2~reg0 ; COMMODITY2~reg0 ; CLK ; CLK ; None ; None ; 1.270 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.s0 ; STATE.s2 ; CLK ; CLK ; None ; None ; 1.171 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.s1 ; STATE.s1 ; CLK ; CLK ; None ; None ; 1.133 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; ERROR2~reg0 ; ERROR2~reg0 ; CLK ; CLK ; None ; None ; 1.105 ns ;
+-------+------------------------------------------------+-------------------+-------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+---------------------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+--------+-------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+--------+-------------------+----------+
; N/A ; None ; 7.706 ns ; DIN[1] ; COMMODITY1~reg0 ; CLK ;
; N/A ; None ; 7.706 ns ; DIN[1] ; GIVE_CHANGE1~reg0 ; CLK ;
; N/A ; None ; 7.482 ns ; DIN[0] ; COMMODITY1~reg0 ; CLK ;
; N/A ; None ; 7.482 ns ; DIN[0] ; GIVE_CHANGE1~reg0 ; CLK ;
; N/A ; None ; 6.884 ns ; DIN[1] ; COMMODITY2~reg0 ; CLK ;
; N/A ; None ; 6.786 ns ; DIN[1] ; ERROR1~reg0 ; CLK ;
; N/A ; None ; 6.496 ns ; DIN[0] ; COMMODITY2~reg0 ; CLK ;
; N/A ; None ; 6.491 ns ; DIN[1] ; STATE.s0 ; CLK ;
; N/A ; None ; 6.393 ns ; DIN[0] ; ERROR1~reg0 ; CLK ;
; N/A ; None ; 6.393 ns ; DIN[1] ; GIVE_CHANGE2~reg0 ; CLK ;
; N/A ; None ; 6.392 ns ; DIN[1] ; ERROR2~reg0 ; CLK ;
; N/A ; None ; 6.369 ns ; DIN[1] ; STATE.s3 ; CLK ;
; N/A ; None ; 6.168 ns ; DIN[0] ; GIVE_CHANGE2~reg0 ; CLK ;
; N/A ; None ; 6.167 ns ; DIN[0] ; ERROR2~reg0 ; CLK ;
; N/A ; None ; 6.041 ns ; DIN[0] ; STATE.s0 ; CLK ;
; N/A ; None ; 5.941 ns ; DIN[1] ; STATE.s2 ; CLK ;
; N/A ; None ; 5.900 ns ; COMM ; COMMODITY1~reg0 ; CLK ;
; N/A ; None ; 5.900 ns ; COMM ; GIVE_CHANGE1~reg0 ; CLK ;
; N/A ; None ; 5.803 ns ; DIN[0] ; STATE.s3 ; CLK ;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -