dzy.tan.qmsg

vhdl编写的自动售货机程序

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK register register STATE.s0 COMMODITY1~reg0 275.03 MHz Internal " "Info: Clock \"CLK\" Internal fmax is restricted to 275.03 MHz between source register \"STATE.s0\" and destination register \"COMMODITY1~reg0\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.052 ns + Longest register register " "Info: + Longest register to register delay is 3.052 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns STATE.s0 1 REG LC_X10_Y2_N0 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y2_N0; Fanout = 10; REG Node = 'STATE.s0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { STATE.s0 } "NODE_NAME" } } { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.580 ns) + CELL(0.114 ns) 0.694 ns COMMODITY1~537 2 COMB LC_X10_Y2_N2 3 " "Info: 2: + IC(0.580 ns) + CELL(0.114 ns) = 0.694 ns; Loc. = LC_X10_Y2_N2; Fanout = 3; COMB Node = 'COMMODITY1~537'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.694 ns" { STATE.s0 COMMODITY1~537 } "NODE_NAME" } } { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.438 ns) + CELL(0.292 ns) 1.424 ns COMMODITY1~540 3 COMB LC_X10_Y2_N7 1 " "Info: 3: + IC(0.438 ns) + CELL(0.292 ns) = 1.424 ns; Loc. = LC_X10_Y2_N7; Fanout = 1; COMB Node = 'COMMODITY1~540'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.730 ns" { COMMODITY1~537 COMMODITY1~540 } "NODE_NAME" } } { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 1.720 ns COMMODITY1~541 4 COMB LC_X10_Y2_N8 2 " "Info: 4: + IC(0.182 ns) + CELL(0.114 ns) = 1.720 ns; Loc. = LC_X10_Y2_N8; Fanout = 2; COMB Node = 'COMMODITY1~541'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { COMMODITY1~540 COMMODITY1~541 } "NODE_NAME" } } { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.465 ns) + CELL(0.867 ns) 3.052 ns COMMODITY1~reg0 5 REG LC_X10_Y2_N1 1 " "Info: 5: + IC(0.465 ns) + CELL(0.867 ns) = 3.052 ns; Loc. = LC_X10_Y2_N1; Fanout = 1; REG Node = 'COMMODITY1~reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.332 ns" { COMMODITY1~541 COMMODITY1~reg0 } "NODE_NAME" } } { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 21 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.387 ns ( 45.45 % ) " "Info: Total cell delay = 1.387 ns ( 45.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.665 ns ( 54.55 % ) " "Info: Total interconnect delay = 1.665 ns ( 54.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.052 ns" { STATE.s0 COMMODITY1~537 COMMODITY1~540 COMMODITY1~541 COMMODITY1~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.052 ns" { STATE.s0 COMMODITY1~537 COMMODITY1~540 COMMODITY1~541 COMMODITY1~reg0 } { 0.000ns 0.580ns 0.438ns 0.182ns 0.465ns } { 0.000ns 0.114ns 0.292ns 0.114ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.733 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.733 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 10 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 10; CLK Node = 'CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.553 ns) + CELL(0.711 ns) 2.733 ns COMMODITY1~reg0 2 REG LC_X10_Y2_N1 1 " "Info: 2: + IC(0.553 ns) + CELL(0.711 ns) = 2.733 ns; Loc. = LC_X10_Y2_N1; Fanout = 1; REG Node = 'COMMODITY1~reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.264 ns" { CLK COMMODITY1~reg0 } "NODE_NAME" } } { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 21 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.77 % ) " "Info: Total cell delay = 2.180 ns ( 79.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.553 ns ( 20.23 % ) " "Info: Total interconnect delay = 0.553 ns ( 20.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.733 ns" { CLK COMMODITY1~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.733 ns" { CLK CLK~out0 COMMODITY1~reg0 } { 0.000ns 0.000ns 0.553ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.733 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.733 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 10 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 10; CLK Node = 'CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.553 ns) + CELL(0.711 ns) 2.733 ns STATE.s0 2 REG LC_X10_Y2_N0 10 " "Info: 2: + IC(0.553 ns) + CELL(0.711 ns) = 2.733 ns; Loc. = LC_X10_Y2_N0; Fanout = 10; REG Node = 'STATE.s0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.264 ns" { CLK STATE.s0 } "NODE_NAME" } } { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.77 % ) " "Info: Total cell delay = 2.180 ns ( 79.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.553 ns ( 20.23 % ) " "Info: Total interconnect delay = 0.553 ns ( 20.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.733 ns" { CLK STATE.s0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.733 ns" { CLK CLK~out0 STATE.s0 } { 0.000ns 0.000ns 0.553ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.733 ns" { CLK COMMODITY1~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.733 ns" { CLK CLK~out0 COMMODITY1~reg0 } { 0.000ns 0.000ns 0.553ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.733 ns" { CLK STATE.s0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.733 ns" { CLK CLK~out0 STATE.s0 } { 0.000ns 0.000ns 0.553ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 21 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.052 ns" { STATE.s0 COMMODITY1~537 COMMODITY1~540 COMMODITY1~541 COMMODITY1~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.052 ns" { STATE.s0 COMMODITY1~537 COMMODITY1~540 COMMODITY1~541 COMMODITY1~reg0 } { 0.000ns 0.580ns 0.438ns 0.182ns 0.465ns } { 0.000ns 0.114ns 0.292ns 0.114ns 0.867ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.733 ns" { CLK COMMODITY1~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.733 ns" { CLK CLK~out0 COMMODITY1~reg0 } { 0.000ns 0.000ns 0.553ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.733 ns" { CLK STATE.s0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.733 ns" { CLK CLK~out0 STATE.s0 } { 0.000ns 0.000ns 0.553ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { COMMODITY1~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { COMMODITY1~reg0 } {  } {  } "" } } { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 21 0 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "COMMODITY1~reg0 DIN\[1\] CLK 7.706 ns register " "Info: tsu for register \"COMMODITY1~reg0\" (data pin = \"DIN\[1\]\", clock pin = \"CLK\") is 7.706 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.402 ns + Longest pin register " "Info: + Longest pin to register delay is 10.402 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns DIN\[1\] 1 PIN PIN_34 17 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_34; Fanout = 17; PIN Node = 'DIN\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DIN[1] } "NODE_NAME" } } { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.300 ns) + CELL(0.442 ns) 7.211 ns Selector9~13 2 COMB LC_X8_Y2_N4 3 " "Info: 2: + IC(5.300 ns) + CELL(0.442 ns) = 7.211 ns; Loc. = LC_X8_Y2_N4; Fanout = 3; COMB Node = 'Selector9~13'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.742 ns" { DIN[1] Selector9~13 } "NODE_NAME" } } { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 104 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.121 ns) + CELL(0.442 ns) 8.774 ns COMMODITY1~540 3 COMB LC_X10_Y2_N7 1 " "Info: 3: + IC(1.121 ns) + CELL(0.442 ns) = 8.774 ns; Loc. = LC_X10_Y2_N7; Fanout = 1; COMB Node = 'COMMODITY1~540'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.563 ns" { Selector9~13 COMMODITY1~540 } "NODE_NAME" } } { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 9.070 ns COMMODITY1~541 4 COMB LC_X10_Y2_N8 2 " "Info: 4: + IC(0.182 ns) + CELL(0.114 ns) = 9.070 ns; Loc. = LC_X10_Y2_N8; Fanout = 2; COMB Node = 'COMMODITY1~541'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { COMMODITY1~540 COMMODITY1~541 } "NODE_NAME" } } { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.465 ns) + CELL(0.867 ns) 10.402 ns COMMODITY1~reg0 5 REG LC_X10_Y2_N1 1 " "Info: 5: + IC(0.465 ns) + CELL(0.867 ns) = 10.402 ns; Loc. = LC_X10_Y2_N1; Fanout = 1; REG Node = 'COMMODITY1~reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.332 ns" { COMMODITY1~541 COMMODITY1~reg0 } "NODE_NAME" } } { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 21 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.334 ns ( 32.05 % ) " "Info: Total cell delay = 3.334 ns ( 32.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.068 ns ( 67.95 % ) " "Info: Total interconnect delay = 7.068 ns ( 67.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.402 ns" { DIN[1] Selector9~13 COMMODITY1~540 COMMODITY1~541 COMMODITY1~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.402 ns" { DIN[1] DIN[1]~out0 Selector9~13 COMMODITY1~540 COMMODITY1~541 COMMODITY1~reg0 } { 0.000ns 0.000ns 5.300ns 1.121ns 0.182ns 0.465ns } { 0.000ns 1.469ns 0.442ns 0.442ns 0.114ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 21 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.733 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.733 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 10 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 10; CLK Node = 'CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.553 ns) + CELL(0.711 ns) 2.733 ns COMMODITY1~reg0 2 REG LC_X10_Y2_N1 1 " "Info: 2: + IC(0.553 ns) + CELL(0.711 ns) = 2.733 ns; Loc. = LC_X10_Y2_N1; Fanout = 1; REG Node = 'COMMODITY1~reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.264 ns" { CLK COMMODITY1~reg0 } "NODE_NAME" } } { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 21 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.77 % ) " "Info: Total cell delay = 2.180 ns ( 79.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.553 ns ( 20.23 % ) " "Info: Total interconnect delay = 0.553 ns ( 20.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.733 ns" { CLK COMMODITY1~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.733 ns" { CLK CLK~out0 COMMODITY1~reg0 } { 0.000ns 0.000ns 0.553ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.402 ns" { DIN[1] Selector9~13 COMMODITY1~540 COMMODITY1~541 COMMODITY1~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.402 ns" { DIN[1] DIN[1]~out0 Selector9~13 COMMODITY1~540 COMMODITY1~541 COMMODITY1~reg0 } { 0.000ns 0.000ns 5.300ns 1.121ns 0.182ns 0.465ns } { 0.000ns 1.469ns 0.442ns 0.442ns 0.114ns 0.867ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.733 ns" { CLK COMMODITY1~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.733 ns" { CLK CLK~out0 COMMODITY1~reg0 } { 0.000ns 0.000ns 0.553ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK COMMODITY1 COMMODITY1~reg0 7.609 ns register " "Info: tco from clock \"CLK\" to destination pin \"COMMODITY1\" through register \"COMMODITY1~reg0\" is 7.609 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.733 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.733 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 10 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 10; CLK Node = 'CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.553 ns) + CELL(0.711 ns) 2.733 ns COMMODITY1~reg0 2 REG LC_X10_Y2_N1 1 " "Info: 2: + IC(0.553 ns) + CELL(0.711 ns) = 2.733 ns; Loc. = LC_X10_Y2_N1; Fanout = 1; REG Node = 'COMMODITY1~reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.264 ns" { CLK COMMODITY1~reg0 } "NODE_NAME" } } { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 21 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.77 % ) " "Info: Total cell delay = 2.180 ns ( 79.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.553 ns ( 20.23 % ) " "Info: Total interconnect delay = 0.553 ns ( 20.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.733 ns" { CLK COMMODITY1~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.733 ns" { CLK CLK~out0 COMMODITY1~reg0 } { 0.000ns 0.000ns 0.553ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 21 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.652 ns + Longest register pin " "Info: + Longest register to pin delay is 4.652 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns COMMODITY1~reg0 1 REG LC_X10_Y2_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y2_N1; Fanout = 1; REG Node = 'COMMODITY1~reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { COMMODITY1~reg0 } "NODE_NAME" } } { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 21 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.528 ns) + CELL(2.124 ns) 4.652 ns COMMODITY1 2 PIN PIN_31 0 " "Info: 2: + IC(2.528 ns) + CELL(2.124 ns) = 4.652 ns; Loc. = PIN_31; Fanout = 0; PIN Node = 'COMMODITY1'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.652 ns" { COMMODITY1~reg0 COMMODITY1 } "NODE_NAME" } } { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 45.66 % ) " "Info: Total cell delay = 2.124 ns ( 45.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.528 ns ( 54.34 % ) " "Info: Total interconnect delay = 2.528 ns ( 54.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.652 ns" { COMMODITY1~reg0 COMMODITY1 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.652 ns" { COMMODITY1~reg0 COMMODITY1 } { 0.000ns 2.528ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.733 ns" { CLK COMMODITY1~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.733 ns" { CLK CLK~out0 COMMODITY1~reg0 } { 0.000ns 0.000ns 0.553ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.652 ns" { COMMODITY1~reg0 COMMODITY1 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.652 ns" { COMMODITY1~reg0 COMMODITY1 } { 0.000ns 2.528ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "GIVE_CHANGE2~reg0 RST CLK -0.719 ns register " "Info: th for register \"GIVE_CHANGE2~reg0\" (data pin = \"RST\", clock pin = \"CLK\") is -0.719 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.733 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 2.733 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 10 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 10; CLK Node = 'CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.553 ns) + CELL(0.711 ns) 2.733 ns GIVE_CHANGE2~reg0 2 REG LC_X11_Y2_N4 3 " "Info: 2: + IC(0.553 ns) + CELL(0.711 ns) = 2.733 ns; Loc. = LC_X11_Y2_N4; Fanout = 3; REG Node = 'GIVE_CHANGE2~reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.264 ns" { CLK GIVE_CHANGE2~reg0 } "NODE_NAME" } } { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 21 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.77 % ) " "Info: Total cell delay = 2.180 ns ( 79.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.553 ns ( 20.23 % ) " "Info: Total interconnect delay = 0.553 ns ( 20.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.733 ns" { CLK GIVE_CHANGE2~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.733 ns" { CLK CLK~out0 GIVE_CHANGE2~reg0 } { 0.000ns 0.000ns 0.553ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 21 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.467 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.467 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns RST 1 PIN PIN_16 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 9; PIN Node = 'RST'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RST } "NODE_NAME" } } { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.131 ns) + CELL(0.867 ns) 3.467 ns GIVE_CHANGE2~reg0 2 REG LC_X11_Y2_N4 3 " "Info: 2: + IC(1.131 ns) + CELL(0.867 ns) = 3.467 ns; Loc. = LC_X11_Y2_N4; Fanout = 3; REG Node = 'GIVE_CHANGE2~reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.998 ns" { RST GIVE_CHANGE2~reg0 } "NODE_NAME" } } { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 21 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns ( 67.38 % ) " "Info: Total cell delay = 2.336 ns ( 67.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.131 ns ( 32.62 % ) " "Info: Total interconnect delay = 1.131 ns ( 32.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.467 ns" { RST GIVE_CHANGE2~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.467 ns" { RST RST~out0 GIVE_CHANGE2~reg0 } { 0.000ns 0.000ns 1.131ns } { 0.000ns 1.469ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.733 ns" { CLK GIVE_CHANGE2~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.733 ns" { CLK CLK~out0 GIVE_CHANGE2~reg0 } { 0.000ns 0.000ns 0.553ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.467 ns" { RST GIVE_CHANGE2~reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.467 ns" { RST RST~out0 GIVE_CHANGE2~reg0 } { 0.000ns 0.000ns 1.131ns } { 0.000ns 1.469ns 0.867ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}