dzy.map.qmsg

vhdl编写的自动售货机程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 28 11:12:27 2007 " "Info: Processing started: Fri Dec 28 11:12:27 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DZY -c DZY " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DZY -c DZY" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SH_MORE.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file SH_MORE.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 SH_MORE-BHV " "Info: Found design unit 1: SH_MORE-BHV" {  } { { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 SH_MORE " "Info: Found entity 1: SH_MORE" {  } { { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SH_Y.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file SH_Y.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 SH_Y-BHV " "Info: Found design unit 1: SH_Y-BHV" {  } { { "SH_Y.vhd" "" { Text "D:/EDA_20044841/20044841/SH_Y.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 SH_Y " "Info: Found entity 1: SH_Y" {  } { { "SH_Y.vhd" "" { Text "D:/EDA_20044841/20044841/SH_Y.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "SH_MORE " "Info: Elaborating entity \"SH_MORE\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|SH_MORE\|STATE 4 " "Info: State machine \"\|SH_MORE\|STATE\" contains 4 states" {  } { { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 17 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|SH_MORE\|STATE " "Info: Selected Auto state machine encoding method for state machine \"\|SH_MORE\|STATE\"" {  } { { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 17 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|SH_MORE\|STATE " "Info: Encoding result for state machine \"\|SH_MORE\|STATE\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "4 " "Info: Completed encoding using 4 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "STATE.s3 " "Info: Encoded state bit \"STATE.s3\"" {  } { { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 17 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "STATE.s2 " "Info: Encoded state bit \"STATE.s2\"" {  } { { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 17 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "STATE.s1 " "Info: Encoded state bit \"STATE.s1\"" {  } { { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 17 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "STATE.s0 " "Info: Encoded state bit \"STATE.s0\"" {  } { { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 17 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|SH_MORE\|STATE.s0 0000 " "Info: State \"\|SH_MORE\|STATE.s0\" uses code string \"0000\"" {  } { { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 17 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|SH_MORE\|STATE.s1 0011 " "Info: State \"\|SH_MORE\|STATE.s1\" uses code string \"0011\"" {  } { { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 17 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|SH_MORE\|STATE.s2 0101 " "Info: State \"\|SH_MORE\|STATE.s2\" uses code string \"0101\"" {  } { { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 17 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|SH_MORE\|STATE.s3 1001 " "Info: State \"\|SH_MORE\|STATE.s3\" uses code string \"1001\"" {  } { { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 17 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0}  } { { "SH_MORE.vhd" "" { Text "D:/EDA_20044841/20044841/SH_MORE.vhd" 17 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "43 " "Info: Implemented 43 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "6 " "Info: Implemented 6 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "32 " "Info: Implemented 32 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "153 " "Info: Allocated 153 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 28 11:12:32 2007 " "Info: Processing ended: Fri Dec 28 11:12:32 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}