dzy.map.rpt

vhdl编写的自动售货机程序

; SH_MORE.vhd                      ; yes             ; User VHDL File  ; D:/EDA_20044841/20044841/SH_MORE.vhd ;
+----------------------------------+-----------------+-----------------+--------------------------------------+


+------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary          ;
+---------------------------------------------+--------+
; Resource                                    ; Usage  ;
+---------------------------------------------+--------+
; Total logic elements                        ; 32     ;
;     -- Combinational with no register       ; 22     ;
;     -- Register only                        ; 0      ;
;     -- Combinational with a register        ; 10     ;
;                                             ;        ;
; Logic element usage by number of LUT inputs ;        ;
;     -- 4 input functions                    ; 21     ;
;     -- 3 input functions                    ; 7      ;
;     -- 2 input functions                    ; 4      ;
;     -- 1 input functions                    ; 0      ;
;     -- 0 input functions                    ; 0      ;
;                                             ;        ;
; Logic elements by mode                      ;        ;
;     -- normal mode                          ; 32     ;
;     -- arithmetic mode                      ; 0      ;
;     -- qfbk mode                            ; 0      ;
;     -- register cascade mode                ; 0      ;
;     -- synchronous clear/load mode          ; 1      ;
;     -- asynchronous clear/load mode         ; 4      ;
;                                             ;        ;
; Total registers                             ; 10     ;
; I/O pins                                    ; 11     ;
; Maximum fan-out node                        ; DIN[1] ;
; Maximum fan-out                             ; 17     ;
; Total fan-out                               ; 141    ;
; Average fan-out                             ; 3.28   ;
+---------------------------------------------+--------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                   ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |SH_MORE                   ; 32 (32)     ; 10           ; 0           ; 11   ; 0            ; 22 (22)      ; 0 (0)             ; 10 (10)          ; 0 (0)           ; 0 (0)      ; |SH_MORE            ; work         ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


Encoding Type:  One-Hot
+------------------------------------------------------+
; State Machine - |SH_MORE|STATE                       ;
+----------+----------+----------+----------+----------+
; Name     ; STATE.s3 ; STATE.s2 ; STATE.s1 ; STATE.s0 ;
+----------+----------+----------+----------+----------+
; STATE.s0 ; 0        ; 0        ; 0        ; 0        ;
; STATE.s1 ; 0        ; 0        ; 1        ; 1        ;
; STATE.s2 ; 0        ; 1        ; 0        ; 1        ;
; STATE.s3 ; 1        ; 0        ; 0        ; 1        ;
+----------+----------+----------+----------+----------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 10    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 1     ;
; Number of registers using Asynchronous Clear ; 4     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 6     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 11:1               ; 2 bits    ; 14 LEs        ; 4 LEs                ; 10 LEs                 ; Yes        ; |SH_MORE|COMMODITY1~reg0   ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Fri Dec 28 11:12:27 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DZY -c DZY
Info: Found 2 design units, including 1 entities, in source file SH_MORE.vhd
    Info: Found design unit 1: SH_MORE-BHV
    Info: Found entity 1: SH_MORE
Info: Found 2 design units, including 1 entities, in source file SH_Y.vhd
    Info: Found design unit 1: SH_Y-BHV
    Info: Found entity 1: SH_Y
Info: Elaborating entity "SH_MORE" for the top level hierarchy
Info: State machine "|SH_MORE|STATE" contains 4 states
Info: Selected Auto state machine encoding method for state machine "|SH_MORE|STATE"
Info: Encoding result for state machine "|SH_MORE|STATE"
    Info: Completed encoding using 4 state bits
        Info: Encoded state bit "STATE.s3"
        Info: Encoded state bit "STATE.s2"
        Info: Encoded state bit "STATE.s1"
        Info: Encoded state bit "STATE.s0"
    Info: State "|SH_MORE|STATE.s0" uses code string "0000"
    Info: State "|SH_MORE|STATE.s1" uses code string "0011"
    Info: State "|SH_MORE|STATE.s2" uses code string "0101"
    Info: State "|SH_MORE|STATE.s3" uses code string "1001"
Info: Implemented 43 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 6 output pins
    Info: Implemented 32 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Allocated 153 megabytes of memory during processing
    Info: Processing ended: Fri Dec 28 11:12:32 2007
    Info: Elapsed time: 00:00:05