dzy.sim.rpt

vhdl编写的自动售货机程序

; |SH_MORE|STATE~617         ; |SH_MORE|STATE~617         ; combout          ;       64.0   ; 169.51 ns          ; 0 ps                       ;
; |SH_MORE|STATE~618         ; |SH_MORE|STATE~618         ; combout          ;       49.0   ; 133.89 ns          ; 0 ps                       ;
; |SH_MORE|STATE~619         ; |SH_MORE|STATE~619         ; combout          ;       46.0   ; 241.18 ns          ; 0 ps                       ;
; |SH_MORE|Selector6~44      ; |SH_MORE|Selector6~44      ; combout          ;       50.0   ; 301.81 ns          ; 0 ps                       ;
; |SH_MORE|STATE~621         ; |SH_MORE|STATE~621         ; combout          ;       10.0   ; 44.46 ns           ; 0 ps                       ;
; |SH_MORE|ERROR1            ; |SH_MORE|ERROR1            ; padio            ;        2.0   ; 10.0 ns            ; 0 ps                       ;
; |SH_MORE|ERROR2            ; |SH_MORE|ERROR2            ; padio            ;        2.0   ; 10.0 ns            ; 0 ps                       ;
; |SH_MORE|COMMODITY1        ; |SH_MORE|COMMODITY1        ; padio            ;       18.0   ; 90.0 ns            ; 0 ps                       ;
; |SH_MORE|COMMODITY2        ; |SH_MORE|COMMODITY2        ; padio            ;       30.0   ; 150.0 ns           ; 0 ps                       ;
; |SH_MORE|GIVE_CHANGE1      ; |SH_MORE|GIVE_CHANGE1      ; padio            ;       12.0   ; 60.0 ns            ; 0 ps                       ;
; |SH_MORE|GIVE_CHANGE2      ; |SH_MORE|GIVE_CHANGE2      ; padio            ;        2.0   ; 10.0 ns            ; 0 ps                       ;
; |SH_MORE|DIN[1]            ; |SH_MORE|DIN[1]            ; input_pad_output ;       49.0   ; 500.0 ns           ; 0 ps                       ;
; |SH_MORE|DIN[0]            ; |SH_MORE|DIN[0]            ; input_pad_output ;       18.0   ; 90.0 ns            ; 0 ps                       ;
; |SH_MORE|COMM              ; |SH_MORE|COMM              ; input_pad_output ;       33.0   ; 490.0 ns           ; 0 ps                       ;
; |SH_MORE|CLK               ; |SH_MORE|CLK               ; input_pad_output ;      199.0   ; 500.0 ns           ; 0 ps                       ;
; |SH_MORE|RST               ; |SH_MORE|RST               ; input_pad_output ;        1.0   ; 10.0 ns            ; 0 ps                       ;
+----------------------------+----------------------------+------------------+--------------+--------------------+----------------------------+


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      97.50 % ;
; Total nodes checked                                 ; 43           ;
; Total output ports checked                          ; 40           ;
; Total output ports with complete 1/0-value coverage ; 39           ;
; Total output ports with no 1/0-value coverage       ; 0            ;
; Total output ports with no 1-value coverage         ; 1            ;
; Total output ports with no 0-value coverage         ; 0            ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+----------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                ;
+----------------------------+----------------------------+------------------+
; Node Name                  ; Output Port Name           ; Output Port Type ;
+----------------------------+----------------------------+------------------+
; |SH_MORE|GIVE_CHANGE2~reg0 ; |SH_MORE|GIVE_CHANGE2~reg0 ; regout           ;
; |SH_MORE|ERROR1~reg0       ; |SH_MORE|ERROR1~reg0       ; regout           ;
; |SH_MORE|COMMODITY1~reg0   ; |SH_MORE|COMMODITY1~reg0   ; regout           ;
; |SH_MORE|GIVE_CHANGE1~reg0 ; |SH_MORE|GIVE_CHANGE1~reg0 ; regout           ;
; |SH_MORE|STATE.s0          ; |SH_MORE|STATE.s0          ; regout           ;
; |SH_MORE|COMMODITY1~537    ; |SH_MORE|COMMODITY1~537    ; combout          ;
; |SH_MORE|ERROR1~310        ; |SH_MORE|ERROR1~310        ; combout          ;
; |SH_MORE|STATE.s2          ; |SH_MORE|STATE.s2          ; regout           ;
; |SH_MORE|COMMODITY2~496    ; |SH_MORE|COMMODITY2~496    ; combout          ;
; |SH_MORE|STATE.s3          ; |SH_MORE|STATE.s3          ; regout           ;
; |SH_MORE|ERROR1~311        ; |SH_MORE|ERROR1~311        ; combout          ;
; |SH_MORE|ERROR1~312        ; |SH_MORE|ERROR1~312        ; combout          ;
; |SH_MORE|ERROR1~313        ; |SH_MORE|ERROR1~313        ; combout          ;
; |SH_MORE|Mux17~28          ; |SH_MORE|Mux17~28          ; combout          ;
; |SH_MORE|COMMODITY1~539    ; |SH_MORE|COMMODITY1~539    ; combout          ;
; |SH_MORE|Selector9~13      ; |SH_MORE|Selector9~13      ; combout          ;
; |SH_MORE|COMMODITY1~540    ; |SH_MORE|COMMODITY1~540    ; combout          ;
; |SH_MORE|COMMODITY1~541    ; |SH_MORE|COMMODITY1~541    ; combout          ;
; |SH_MORE|COMMODITY2~497    ; |SH_MORE|COMMODITY2~497    ; combout          ;
; |SH_MORE|COMMODITY2~498    ; |SH_MORE|COMMODITY2~498    ; combout          ;
; |SH_MORE|COMMODITY2~499    ; |SH_MORE|COMMODITY2~499    ; combout          ;
; |SH_MORE|Selector9~14      ; |SH_MORE|Selector9~14      ; combout          ;
; |SH_MORE|GIVE_CHANGE2~74   ; |SH_MORE|GIVE_CHANGE2~74   ; combout          ;
; |SH_MORE|STATE~616         ; |SH_MORE|STATE~616         ; combout          ;
; |SH_MORE|STATE~617         ; |SH_MORE|STATE~617         ; combout          ;
; |SH_MORE|STATE~618         ; |SH_MORE|STATE~618         ; combout          ;
; |SH_MORE|STATE~619         ; |SH_MORE|STATE~619         ; combout          ;
; |SH_MORE|Selector6~44      ; |SH_MORE|Selector6~44      ; combout          ;
; |SH_MORE|STATE~621         ; |SH_MORE|STATE~621         ; combout          ;
; |SH_MORE|ERROR1            ; |SH_MORE|ERROR1            ; padio            ;
; |SH_MORE|ERROR2            ; |SH_MORE|ERROR2            ; padio            ;
; |SH_MORE|COMMODITY1        ; |SH_MORE|COMMODITY1        ; padio            ;
; |SH_MORE|COMMODITY2        ; |SH_MORE|COMMODITY2        ; padio            ;
; |SH_MORE|GIVE_CHANGE1      ; |SH_MORE|GIVE_CHANGE1      ; padio            ;
; |SH_MORE|GIVE_CHANGE2      ; |SH_MORE|GIVE_CHANGE2      ; padio            ;
; |SH_MORE|DIN[1]            ; |SH_MORE|DIN[1]~corein     ; combout          ;
; |SH_MORE|DIN[0]            ; |SH_MORE|DIN[0]~corein     ; combout          ;
; |SH_MORE|COMM              ; |SH_MORE|COMM~corein       ; combout          ;
; |SH_MORE|CLK               ; |SH_MORE|CLK~corein        ; combout          ;
+----------------------------+----------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+-------------------------------------------------------+
; Missing 1-Value Coverage                              ;
+--------------+---------------------+------------------+
; Node Name    ; Output Port Name    ; Output Port Type ;
+--------------+---------------------+------------------+
; |SH_MORE|RST ; |SH_MORE|RST~corein ; combout          ;
+--------------+---------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+-------------------------------------------------+
; Missing 0-Value Coverage                        ;
+-----------+------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-----------+------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Fri Dec 28 10:04:57 2007
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off DZY -c DZY
Info: Using vector source file "D:/EDA_20044841/20044841/SH_MORE.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Created Signal Activity File D:/EDA_20044841/20044841/DZY.saf
Info: Simulation coverage is      97.50 %
Info: Number of transitions in simulation is 1596
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Allocated 93 megabytes of memory during processing
    Info: Processing ended: Fri Dec 28 10:04:59 2007
    Info: Elapsed time: 00:00:02