dzy.saf

vhdl编写的自动售货机程序

# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.

# Signal Activity File Name: "D:/EDA_20044841/20044841/DZY.saf"
# Created On: "12/28/2007 10:04:58"
# Created By: "Version 7.1 Build 156 04/30/2007 SJ Full Version"
# This file was created by the Quartus(R) II Simulator with glitch filtering enabled.

FORMAT_VERSION 1;

DEFINE_FLAG TOGGLE_RATE_FROM_SIMULATION 0x1;
DEFINE_FLAG STATIC_PROBABILITY_FROM_SIMULATION 0x2;
DEFINE_FLAG TOGGLE_RATE_FROM_USER 0x4;
DEFINE_FLAG STATIC_PROBABILITY_FROM_USER 0x8;
DEFINE_FLAG TOGGLE_RATE_FROM_USER_DEFAULT 0x10;
DEFINE_FLAG STATIC_PROBABILITY_FROM_USER_DEFAULT 0x20;
DEFINE_FLAG TOGGLE_RATE_FROM_VECTORLESS_ESTIMATION 0x40;
DEFINE_FLAG STATIC_PROBABILITY_FROM_VECTORLESS_ESTIMATION 0x80;
DEFINE_FLAG TOGGLE_RATE_ASSUMED_ZERO 0x100;
DEFINE_FLAG TOGGLE_RATE_CLIPPED_TO_MAX 0x200;

BEGIN_OUTPUT_SIGNAL_INFO;

# Output Signal Information Line Format Description:

# <one or more spaces><partial output signal name><spaces>[<flags mask><spaces><toggle rate><spaces><static probability>]<;>

 CLK 0x3 1.99e+008 0.5;
 COMM 0x3 3.3e+007 0.49;
 COMMODITY1 0x3 1.8e+007 0.09;
 COMMODITY1~537 0x3 8e+006 0.011801;
 COMMODITY1~539 0x3 5.8e+007 0.349309;
 COMMODITY1~540 0x3 6e+007 0.369975;
 COMMODITY1~541 0x3 5.9e+007 0.459232;
 COMMODITY1~reg0 0x3 1.8e+007 0.09;
 COMMODITY2 0x3 3e+007 0.15;
 COMMODITY2~496 0x3 5.2e+007 0.41;
 COMMODITY2~497 0x3 5.6e+007 0.632624;
 COMMODITY2~498 0x3 8e+006 0.030825;
 COMMODITY2~499 0x3 5.6e+007 0.242296;
 COMMODITY2~reg0 0x3 3.1e+007 0.152043;
 DIN[0] 0x3 1.8e+007 0.09;
 DIN[1] 0x3 4.9e+007 0.5;
 ERROR1 0x3 2e+006 0.01;
 ERROR1~310 0x3 5.8e+007 0.641802;
 ERROR1~311 0x3 8.7e+007 0.534706;
 ERROR1~312 0x3 1.4e+007 0.051929;
 ERROR1~313 0x3 1.2e+007 0.025917;
 ERROR1~reg0 0x3 2e+006 0.01;
 ERROR2 0x3 2e+006 0.01;
 ERROR2~reg0 0x3 2e+006 0.01;
 GIVE_CHANGE1 0x3 1.2e+007 0.06;
 GIVE_CHANGE1~reg0 0x3 1.2e+007 0.06;
 GIVE_CHANGE2 0x3 2e+006 0.01;
 GIVE_CHANGE2~74 0x3 2e+006 0.000253;
 GIVE_CHANGE2~reg0 0x3 2e+006 0.01;
 Mux17~28 0x3 4e+006 0.020225;
 RST 0x3 1e+006 0.01;
 Selector6~44 0x3 5e+007 0.301808;
 Selector9~13 0x3 4.9e+007 0.473685;
 Selector9~14 0x3 8e+006 0.040011;
 STATE.s0 0x3 5.2e+007 0.63;
 STATE.s1 0x3 6e+006 0.04;
 STATE.s2 0x3 4.6e+007 0.55;
 STATE.s3 0x3 6e+006 0.04;
 STATE~616 0x3 1.13e+008 0.452855;
 STATE~617 0x3 6.4e+007 0.169513;
 STATE~618 0x3 4.9e+007 0.133893;
 STATE~619 0x3 4.6e+007 0.24118;
 STATE~621 0x3 1e+007 0.044455;

END_OUTPUT_SIGNAL_INFO;

TOGGLE_PERCENTAGE 100;

PERCENTAGE_OF_TIME_SIGNALS_IN_UNKNOWN_STATE 0;