sh_y.vhd

vhdl编写的自动售货机程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SH_Y IS
	PORT(		
		CLK:IN STD_LOGIC;							--输入端口
		RST:IN STD_LOGIC;
		DIN:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
		ERROR:OUT STD_LOGIC;						--输出端口
		COMMODITY:OUT STD_LOGIC;
		GIVE_CHANGE:OUT STD_LOGIC
		);
END;
ARCHITECTURE BHV OF SH_Y IS
	TYPE FSM_ST IS (S0,S1,S2,S3);					--定义状态数据类型
	SIGNAL STATE:FSM_ST;							--定义状态数据信号
BEGIN
	PROCESS(CLK,RST)
	BEGIN
	IF RST='1' THEN STATE<=S0;						--高电平置位
	ELSIF CLK'EVENT AND CLK='1' THEN				--时钟上升沿
	CASE STATE IS									--状态判断和转换
		WHEN S0=>
			CASE DIN IS
				WHEN "00"=>STATE<=S0;				--售出商品后的初始化语句
COMMODITY<='0';
GIVE_CHANGE<='0';
ERROR<='0';
				WHEN "01"=>STATE<=S1;				--售出商品后的初始化语句
COMMODITY<='0';
GIVE_CHANGE<='0';
ERROR<='0';
				WHEN "10"=>STATE<=S2;				--售出商品后的初始化语句
COMMODITY<='0';
GIVE_CHANGE<='0';
ERROR<='0';
				WHEN "11"=>COMMODITY<='1';			--投入5元时送出商品
GIVE_CHANGE<='1';									--找