qiangda.rpt

两人抢答器,有抢答,倒计时,记分,响铃功能.

        | | | +------------------- LC19 mark11
        | | | | +----------------- LC18 mark12
        | | | | | +--------------- LC17 mark13
        | | | | | | +------------- LC21 mark14
        | | | | | | | +----------- LC30 mark20
        | | | | | | | | +--------- LC29 mark21
        | | | | | | | | | +------- LC25 mark22
        | | | | | | | | | | +----- LC24 mark23
        | | | | | | | | | | | +--- LC23 mark24
        | | | | | | | | | | | | +- LC22 ring
        | | | | | | | | | | | | | 
        | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC31 -> * - - - - - - - - - - - - | - * | <-- led0
LC32 -> - * - - - - - - - - - - - | - * | <-- led1
LC20 -> - - * - - - - - - - - - - | - * | <-- mark10
LC19 -> - - - * - - - - - - - - - | - * | <-- mark11
LC18 -> - - - - * - - - - - - - - | - * | <-- mark12
LC17 -> - - - - - * - - - - - - - | - * | <-- mark13
LC21 -> - - - - - - * - - - - - - | - * | <-- mark14
LC30 -> - - - - - - - * - - - - - | - * | <-- mark20
LC29 -> - - - - - - - - * - - - - | - * | <-- mark21
LC25 -> - - - - - - - - - * - - - | - * | <-- mark22
LC24 -> - - - - - - - - - - * - - | - * | <-- mark23
LC23 -> - - - - - - - - - - - * - | - * | <-- mark24
LC22 -> - - - - - - - - - - - - * | - * | <-- ring

Pin
4    -> - - - * * * * - * * * * - | - * | <-- answer
43   -> - - - - - - - - - - - - - | - - | <-- clk
8    -> * - * * * * * - - - - - * | - * | <-- clr_1
9    -> - * - - - - - * * * * * * | - * | <-- clr_2
6    -> * * * * * * * * * * * * * | - * | <-- sel0
5    -> * * * * * * * * * * * * * | - * | <-- sel1
7    -> * * * * * * * * * * * * * | - * | <-- start


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                          d:\qiangdaqi\qiangda.rpt
qiangda

** EQUATIONS **

answer   : INPUT;
clk      : INPUT;
clr_1    : INPUT;
clr_2    : INPUT;
sel0     : INPUT;
sel1     : INPUT;
start    : INPUT;

-- Node name is 'led0' = ':10' 
-- Equation name is 'led0', type is output 
 led0    = DFFE( _EQ001 $  GND, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ001 =  clr_1 &  sel0 & !sel1 &  start
         #  led0 & !start;

-- Node name is 'led1' = ':8' 
-- Equation name is 'led1', type is output 
 led1    = DFFE( _EQ002 $  GND, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ002 =  clr_2 & !sel0 &  sel1 &  start
         #  led1 & !start;

-- Node name is 'mark10' = 'bb0' 
-- Equation name is 'mark10', location is LC020, type is output.
 mark10  = TFFE( _EQ003, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ003 = !clr_1 &  mark10 &  sel0 & !sel1 &  start;

-- Node name is 'mark11' = 'bb1' 
-- Equation name is 'mark11', location is LC019, type is output.
 mark11  = TFFE( _EQ004, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ004 =  answer & !clr_1 & !mark11 &  sel0 & !sel1 &  start
         # !answer & !clr_1 &  mark11 &  sel0 & !sel1 &  start;

-- Node name is 'mark12' = 'bb2' 
-- Equation name is 'mark12', location is LC018, type is output.
 mark12  = TFFE( _EQ005, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ005 =  answer & !clr_1 & !mark12 &  sel0 & !sel1 &  start
         # !answer & !clr_1 &  mark12 &  sel0 & !sel1 &  start;

-- Node name is 'mark13' = 'bb3' 
-- Equation name is 'mark13', location is LC017, type is output.
 mark13  = TFFE( _EQ006, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ006 =  answer & !clr_1 & !mark13 &  sel0 & !sel1 &  start
         # !answer & !clr_1 &  mark13 &  sel0 & !sel1 &  start;

-- Node name is 'mark14' = 'bb4' 
-- Equation name is 'mark14', location is LC021, type is output.
 mark14  = TFFE( _EQ007, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ007 =  answer & !clr_1 & !mark14 &  sel0 & !sel1 &  start
         # !answer & !clr_1 &  mark14 &  sel0 & !sel1 &  start;

-- Node name is 'mark20' = 'cc0' 
-- Equation name is 'mark20', location is LC030, type is output.
 mark20  = TFFE( _EQ008, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ008 = !clr_2 &  mark20 & !sel0 &  sel1 &  start;

-- Node name is 'mark21' = 'cc1' 
-- Equation name is 'mark21', location is LC029, type is output.
 mark21  = TFFE( _EQ009, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ009 =  answer & !clr_2 & !mark21 & !sel0 &  sel1 &  start
         # !answer & !clr_2 &  mark21 & !sel0 &  sel1 &  start;

-- Node name is 'mark22' = 'cc2' 
-- Equation name is 'mark22', location is LC025, type is output.
 mark22  = TFFE( _EQ010, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ010 =  answer & !clr_2 & !mark22 & !sel0 &  sel1 &  start
         # !answer & !clr_2 &  mark22 & !sel0 &  sel1 &  start;

-- Node name is 'mark23' = 'cc3' 
-- Equation name is 'mark23', location is LC024, type is output.
 mark23  = TFFE( _EQ011, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ011 =  answer & !clr_2 & !mark23 & !sel0 &  sel1 &  start
         # !answer & !clr_2 &  mark23 & !sel0 &  sel1 &  start;

-- Node name is 'mark24' = 'cc4' 
-- Equation name is 'mark24', location is LC023, type is output.
 mark24  = TFFE( _EQ012, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ012 =  answer & !clr_2 & !mark24 & !sel0 &  sel1 &  start
         # !answer & !clr_2 &  mark24 & !sel0 &  sel1 &  start;

-- Node name is 'ring' = ':12' 
-- Equation name is 'ring', type is output 
 ring    = TFFE( _EQ013, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ013 =  clr_2 & !ring & !sel0 &  sel1 &  start
         #  clr_1 & !ring &  sel0 & !sel1 &  start;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                   d:\qiangdaqi\qiangda.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,340K