cnt100.sim.rpt

基于VHDL的8位十进制频率计的详细设计。

; |CNT|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] ; |CNT|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] ; sout             ;
+--------------------------------------------------------------------------+--------------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+--------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                                             ;
+---------------------------------------------------------+---------------------------------------------------------+------------------+
; Node Name                                               ; Output Port Name                                        ; Output Port Type ;
+---------------------------------------------------------+---------------------------------------------------------+------------------+
; |CNT|q_tmp[7]                                           ; |CNT|q_tmp[7]                                           ; regout           ;
; |CNT|q_bcd[7]                                           ; |CNT|q_bcd[7]                                           ; pin_out          ;
; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0     ; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0     ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[0]       ; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[0]       ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|_~1                 ; |CNT|lpm_add_sub:Add0|addcore:adder|_~1                 ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|_~2                 ; |CNT|lpm_add_sub:Add0|addcore:adder|_~2                 ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[7]~1     ; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[7]~1     ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[7]       ; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[7]       ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[6]       ; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[6]       ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[5]       ; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[5]       ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[4]       ; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[4]       ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[3]       ; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[3]       ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[2]       ; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[2]       ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[1]       ; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[1]       ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7]~1 ; |CNT|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7]~1 ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|_~4                 ; |CNT|lpm_add_sub:Add0|addcore:adder|_~4                 ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|_~5                 ; |CNT|lpm_add_sub:Add0|addcore:adder|_~5                 ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|_~6                 ; |CNT|lpm_add_sub:Add0|addcore:adder|_~6                 ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|_~7                 ; |CNT|lpm_add_sub:Add0|addcore:adder|_~7                 ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|_~8                 ; |CNT|lpm_add_sub:Add0|addcore:adder|_~8                 ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|_~9                 ; |CNT|lpm_add_sub:Add0|addcore:adder|_~9                 ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|_~10                ; |CNT|lpm_add_sub:Add0|addcore:adder|_~10                ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|_~11                ; |CNT|lpm_add_sub:Add0|addcore:adder|_~11                ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|_~18                ; |CNT|lpm_add_sub:Add0|addcore:adder|_~18                ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|_~25                ; |CNT|lpm_add_sub:Add0|addcore:adder|_~25                ; out0             ;
+---------------------------------------------------------+---------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+--------------------------------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage                                                                                                             ;
+---------------------------------------------------------+---------------------------------------------------------+------------------+
; Node Name                                               ; Output Port Name                                        ; Output Port Type ;
+---------------------------------------------------------+---------------------------------------------------------+------------------+
; |CNT|q_tmp[7]                                           ; |CNT|q_tmp[7]                                           ; regout           ;
; |CNT|q_bcd[7]                                           ; |CNT|q_bcd[7]                                           ; pin_out          ;
; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0     ; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0     ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[0]       ; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[0]       ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|_~1                 ; |CNT|lpm_add_sub:Add0|addcore:adder|_~1                 ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|_~2                 ; |CNT|lpm_add_sub:Add0|addcore:adder|_~2                 ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[7]~1     ; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[7]~1     ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[7]       ; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[7]       ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[6]       ; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[6]       ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[5]       ; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[5]       ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[4]       ; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[4]       ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[3]       ; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[3]       ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[2]       ; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[2]       ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[1]       ; |CNT|lpm_add_sub:Add0|addcore:adder|datab_node[1]       ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7]~1 ; |CNT|lpm_add_sub:Add0|addcore:adder|unreg_res_node[7]~1 ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|_~4                 ; |CNT|lpm_add_sub:Add0|addcore:adder|_~4                 ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|_~5                 ; |CNT|lpm_add_sub:Add0|addcore:adder|_~5                 ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|_~6                 ; |CNT|lpm_add_sub:Add0|addcore:adder|_~6                 ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|_~7                 ; |CNT|lpm_add_sub:Add0|addcore:adder|_~7                 ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|_~8                 ; |CNT|lpm_add_sub:Add0|addcore:adder|_~8                 ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|_~9                 ; |CNT|lpm_add_sub:Add0|addcore:adder|_~9                 ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|_~10                ; |CNT|lpm_add_sub:Add0|addcore:adder|_~10                ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|_~11                ; |CNT|lpm_add_sub:Add0|addcore:adder|_~11                ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|_~18                ; |CNT|lpm_add_sub:Add0|addcore:adder|_~18                ; out0             ;
; |CNT|lpm_add_sub:Add0|addcore:adder|_~25                ; |CNT|lpm_add_sub:Add0|addcore:adder|_~25                ; out0             ;
+---------------------------------------------------------+---------------------------------------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Tue Dec 25 16:27:33 2007
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off CNT100 -c CNT100
Info: Using vector source file "E:/EDA/实验七/Waveform1.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      78.07 %
Info: Number of transitions in simulation is 22733
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Allocated 93 megabytes of memory during processing
    Info: Processing ended: Tue Dec 25 16:27:35 2007
    Info: Elapsed time: 00:00:02