reg4b.vhd

来自「基于VHDL的4位带异步清零的二进制计数器。」· VHDL 代码 · 共 16 行

LIBRARY IEEE;  --4位锁存器
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG4B IS
    PORT (  LOAD : IN STD_LOGIC;
             DIN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
            DOUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );
END REG4B;
ARCHITECTURE behav OF REG4B IS
BEGIN
 PROCESS(LOAD, DIN)
BEGIN
  IF LOAD'EVENT AND LOAD = '1' THEN  DOUT <= DIN; --时钟到来时，锁存输入数据
   END IF;
 END PROCESS;
END behav;