📄 prev_cmp_deccounter.tan.qmsg
字号:
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "10 " "Warning: Found 10 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "CNT4B:inst6\|COUT " "Info: Detected gated clock \"CNT4B:inst6\|COUT\" as buffer" { } { { "CNT4B.vhd" "" { Text "E:/EDA/实验六/CNT4B.vhd" 9 -1 0 } } { "e:/eda/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "CNT4B:inst6\|COUT" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "CNT4B:inst5\|COUT " "Info: Detected gated clock \"CNT4B:inst5\|COUT\" as buffer" { } { { "CNT4B.vhd" "" { Text "E:/EDA/实验六/CNT4B.vhd" 9 -1 0 } } { "e:/eda/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "CNT4B:inst5\|COUT" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "CNT4B:inst\|COUT " "Info: Detected gated clock \"CNT4B:inst\|COUT\" as buffer" { } { { "CNT4B.vhd" "" { Text "E:/EDA/实验六/CNT4B.vhd" 9 -1 0 } } { "e:/eda/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "CNT4B:inst\|COUT" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "CNT4B:inst6\|CQI\[0\] " "Info: Detected ripple clock \"CNT4B:inst6\|CQI\[0\]\" as buffer" { } { { "CNT4B.vhd" "" { Text "E:/EDA/实验六/CNT4B.vhd" 16 -1 0 } } { "e:/eda/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "CNT4B:inst6\|CQI\[0\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "CNT4B:inst6\|CQI\[3\] " "Info: Detected ripple clock \"CNT4B:inst6\|CQI\[3\]\" as buffer" { } { { "CNT4B.vhd" "" { Text "E:/EDA/实验六/CNT4B.vhd" 16 -1 0 } } { "e:/eda/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "CNT4B:inst6\|CQI\[3\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "CNT4B:inst5\|CQI\[0\] " "Info: Detected ripple clock \"CNT4B:inst5\|CQI\[0\]\" as buffer" { } { { "CNT4B.vhd" "" { Text "E:/EDA/实验六/CNT4B.vhd" 16 -1 0 } } { "e:/eda/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "CNT4B:inst5\|CQI\[0\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "CNT4B:inst5\|CQI\[3\] " "Info: Detected ripple clock \"CNT4B:inst5\|CQI\[3\]\" as buffer" { } { { "CNT4B.vhd" "" { Text "E:/EDA/实验六/CNT4B.vhd" 16 -1 0 } } { "e:/eda/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "CNT4B:inst5\|CQI\[3\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "CNT4B:inst\|CQI\[0\] " "Info: Detected ripple clock \"CNT4B:inst\|CQI\[0\]\" as buffer" { } { { "CNT4B.vhd" "" { Text "E:/EDA/实验六/CNT4B.vhd" 16 -1 0 } } { "e:/eda/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "CNT4B:inst\|CQI\[0\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "TESTCTL:inst8\|DIV2CLK " "Info: Detected ripple clock \"TESTCTL:inst8\|DIV2CLK\" as buffer" { } { { "TESTCTL.vhd" "" { Text "E:/EDA/实验六/TESTCTL.vhd" 13 -1 0 } } { "e:/eda/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "TESTCTL:inst8\|DIV2CLK" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "CNT4B:inst\|CQI\[3\] " "Info: Detected ripple clock \"CNT4B:inst\|CQI\[3\]\" as buffer" { } { { "CNT4B.vhd" "" { Text "E:/EDA/实验六/CNT4B.vhd" 16 -1 0 } } { "e:/eda/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "CNT4B:inst\|CQI\[3\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLKK register register TESTCTL:inst8\|DIV2CLK TESTCTL:inst8\|DIV2CLK 275.03 MHz Internal " "Info: Clock \"CLKK\" Internal fmax is restricted to 275.03 MHz between source register \"TESTCTL:inst8\|DIV2CLK\" and destination register \"TESTCTL:inst8\|DIV2CLK\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.822 ns + Longest register register " "Info: + Longest register to register delay is 0.822 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns TESTCTL:inst8\|DIV2CLK 1 REG LC_X8_Y6_N0 37 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y6_N0; Fanout = 37; REG Node = 'TESTCTL:inst8\|DIV2CLK'" { } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "" { TESTCTL:inst8|DIV2CLK } "NODE_NAME" } } { "TESTCTL.vhd" "" { Text "E:/EDA/实验六/TESTCTL.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.513 ns) + CELL(0.309 ns) 0.822 ns TESTCTL:inst8\|DIV2CLK 2 REG LC_X8_Y6_N0 37 " "Info: 2: + IC(0.513 ns) + CELL(0.309 ns) = 0.822 ns; Loc. = LC_X8_Y6_N0; Fanout = 37; REG Node = 'TESTCTL:inst8\|DIV2CLK'" { } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "0.822 ns" { TESTCTL:inst8|DIV2CLK TESTCTL:inst8|DIV2CLK } "NODE_NAME" } } { "TESTCTL.vhd" "" { Text "E:/EDA/实验六/TESTCTL.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns ( 37.59 % ) " "Info: Total cell delay = 0.309 ns ( 37.59 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.513 ns ( 62.41 % ) " "Info: Total interconnect delay = 0.513 ns ( 62.41 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "0.822 ns" { TESTCTL:inst8|DIV2CLK TESTCTL:inst8|DIV2CLK } "NODE_NAME" } } { "e:/eda/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/eda/quartus/bin/Technology_Viewer.qrui" "0.822 ns" { TESTCTL:inst8|DIV2CLK TESTCTL:inst8|DIV2CLK } { 0.000ns 0.513ns } { 0.000ns 0.309ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLKK destination 3.903 ns + Shortest register " "Info: + Shortest clock path from clock \"CLKK\" to destination register is 3.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns CLKK 1 CLK PIN_47 5 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_47; Fanout = 5; CLK Node = 'CLKK'" { } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLKK } "NODE_NAME" } } { "deccounter.bdf" "" { Schematic "E:/EDA/实验六/deccounter.bdf" { { 120 -88 80 136 "CLKK" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.717 ns) + CELL(0.711 ns) 3.903 ns TESTCTL:inst8\|DIV2CLK 2 REG LC_X8_Y6_N0 37 " "Info: 2: + IC(1.717 ns) + CELL(0.711 ns) = 3.903 ns; Loc. = LC_X8_Y6_N0; Fanout = 37; REG Node = 'TESTCTL:inst8\|DIV2CLK'" { } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "2.428 ns" { CLKK TESTCTL:inst8|DIV2CLK } "NODE_NAME" } } { "TESTCTL.vhd" "" { Text "E:/EDA/实验六/TESTCTL.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 56.01 % ) " "Info: Total cell delay = 2.186 ns ( 56.01 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.717 ns ( 43.99 % ) " "Info: Total interconnect delay = 1.717 ns ( 43.99 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "3.903 ns" { CLKK TESTCTL:inst8|DIV2CLK } "NODE_NAME" } } { "e:/eda/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/eda/quartus/bin/Technology_Viewer.qrui" "3.903 ns" { CLKK CLKK~out0 TESTCTL:inst8|DIV2CLK } { 0.000ns 0.000ns 1.717ns } { 0.000ns 1.475ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLKK source 3.903 ns - Longest register " "Info: - Longest clock path from clock \"CLKK\" to source register is 3.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns CLKK 1 CLK PIN_47 5 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_47; Fanout = 5; CLK Node = 'CLKK'" { } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLKK } "NODE_NAME" } } { "deccounter.bdf" "" { Schematic "E:/EDA/实验六/deccounter.bdf" { { 120 -88 80 136 "CLKK" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.717 ns) + CELL(0.711 ns) 3.903 ns TESTCTL:inst8\|DIV2CLK 2 REG LC_X8_Y6_N0 37 " "Info: 2: + IC(1.717 ns) + CELL(0.711 ns) = 3.903 ns; Loc. = LC_X8_Y6_N0; Fanout = 37; REG Node = 'TESTCTL:inst8\|DIV2CLK'" { } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "2.428 ns" { CLKK TESTCTL:inst8|DIV2CLK } "NODE_NAME" } } { "TESTCTL.vhd" "" { Text "E:/EDA/实验六/TESTCTL.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 56.01 % ) " "Info: Total cell delay = 2.186 ns ( 56.01 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.717 ns ( 43.99 % ) " "Info: Total interconnect delay = 1.717 ns ( 43.99 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "3.903 ns" { CLKK TESTCTL:inst8|DIV2CLK } "NODE_NAME" } } { "e:/eda/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/eda/quartus/bin/Technology_Viewer.qrui" "3.903 ns" { CLKK CLKK~out0 TESTCTL:inst8|DIV2CLK } { 0.000ns 0.000ns 1.717ns } { 0.000ns 1.475ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "3.903 ns" { CLKK TESTCTL:inst8|DIV2CLK } "NODE_NAME" } } { "e:/eda/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/eda/quartus/bin/Technology_Viewer.qrui" "3.903 ns" { CLKK CLKK~out0 TESTCTL:inst8|DIV2CLK } { 0.000ns 0.000ns 1.717ns } { 0.000ns 1.475ns 0.711ns } "" } } { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "3.903 ns" { CLKK TESTCTL:inst8|DIV2CLK } "NODE_NAME" } } { "e:/eda/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/eda/quartus/bin/Technology_Viewer.qrui" "3.903 ns" { CLKK CLKK~out0 TESTCTL:inst8|DIV2CLK } { 0.000ns 0.000ns 1.717ns } { 0.000ns 1.475ns 0.711ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "TESTCTL.vhd" "" { Text "E:/EDA/实验六/TESTCTL.vhd" 13 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "TESTCTL.vhd" "" { Text "E:/EDA/实验六/TESTCTL.vhd" 13 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "0.822 ns" { TESTCTL:inst8|DIV2CLK TESTCTL:inst8|DIV2CLK } "NODE_NAME" } } { "e:/eda/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/eda/quartus/bin/Technology_Viewer.qrui" "0.822 ns" { TESTCTL:inst8|DIV2CLK TESTCTL:inst8|DIV2CLK } { 0.000ns 0.513ns } { 0.000ns 0.309ns } "" } } { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "3.903 ns" { CLKK TESTCTL:inst8|DIV2CLK } "NODE_NAME" } } { "e:/eda/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/eda/quartus/bin/Technology_Viewer.qrui" "3.903 ns" { CLKK CLKK~out0 TESTCTL:inst8|DIV2CLK } { 0.000ns 0.000ns 1.717ns } { 0.000ns 1.475ns 0.711ns } "" } } { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "3.903 ns" { CLKK TESTCTL:inst8|DIV2CLK } "NODE_NAME" } } { "e:/eda/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/eda/quartus/bin/Technology_Viewer.qrui" "3.903 ns" { CLKK CLKK~out0 TESTCTL:inst8|DIV2CLK } { 0.000ns 0.000ns 1.717ns } { 0.000ns 1.475ns 0.711ns } "" } } } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0} } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "" { TESTCTL:inst8|DIV2CLK } "NODE_NAME" } } { "e:/eda/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/eda/quartus/bin/Technology_Viewer.qrui" "" { TESTCTL:inst8|DIV2CLK } { } { } "" } } { "TESTCTL.vhd" "" { Text "E:/EDA/实验六/TESTCTL.vhd" 13 -1 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK register register CNT4B:inst7\|CQI\[3\] CNT4B:inst7\|CQI\[3\] 275.03 MHz Internal " "Info: Clock \"CLK\" Internal fmax is restricted to 275.03 MHz between source register \"CNT4B:inst7\|CQI\[3\]\" and destination register \"CNT4B:inst7\|CQI\[3\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.260 ns + Longest register register " "Info: + Longest register to register delay is 1.260 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CNT4B:inst7\|CQI\[3\] 1 REG LC_X23_Y8_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y8_N2; Fanout = 3; REG Node = 'CNT4B:inst7\|CQI\[3\]'" { } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "" { CNT4B:inst7|CQI[3] } "NODE_NAME" } } { "CNT4B.vhd" "" { Text "E:/EDA/实验六/CNT4B.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.522 ns) + CELL(0.738 ns) 1.260 ns CNT4B:inst7\|CQI\[3\] 2 REG LC_X23_Y8_N2 3 " "Info: 2: + IC(0.522 ns) + CELL(0.738 ns) = 1.260 ns; Loc. = LC_X23_Y8_N2; Fanout = 3; REG Node = 'CNT4B:inst7\|CQI\[3\]'" { } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "1.260 ns" { CNT4B:inst7|CQI[3] CNT4B:inst7|CQI[3] } "NODE_NAME" } } { "CNT4B.vhd" "" { Text "E:/EDA/实验六/CNT4B.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.738 ns ( 58.57 % ) " "Info: Total cell delay = 0.738 ns ( 58.57 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.522 ns ( 41.43 % ) " "Info: Total interconnect delay = 0.522 ns ( 41.43 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "1.260 ns" { CNT4B:inst7|CQI[3] CNT4B:inst7|CQI[3] } "NODE_NAME" } } { "e:/eda/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/eda/quartus/bin/Technology_Viewer.qrui" "1.260 ns" { CNT4B:inst7|CQI[3] CNT4B:inst7|CQI[3] } { 0.000ns 0.522ns } { 0.000ns 0.738ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.540 ns - Smallest " "Info: - Smallest clock skew is -0.540 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 20.104 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 20.104 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 4; CLK Node = 'CLK'" { } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "deccounter.bdf" "" { Schematic "E:/EDA/实验六/deccounter.bdf" { { 24 -88 80 40 "CLK" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.935 ns) 3.006 ns CNT4B:inst\|CQI\[3\] 2 REG LC_X26_Y7_N6 4 " "Info: 2: + IC(0.602 ns) + CELL(0.935 ns) = 3.006 ns; Loc. = LC_X26_Y7_N6; Fanout = 4; REG Node = 'CNT4B:inst\|CQI\[3\]'" { } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "1.537 ns" { CLK CNT4B:inst|CQI[3] } "NODE_NAME" } } { "CNT4B.vhd" "" { Text "E:/EDA/实验六/CNT4B.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.536 ns) + CELL(0.114 ns) 3.656 ns CNT4B:inst\|COUT 3 COMB LC_X26_Y7_N4 4 " "Info: 3: + IC(0.536 ns) + CELL(0.114 ns) = 3.656 ns; Loc. = LC_X26_Y7_N4; Fanout = 4; COMB Node = 'CNT4B:inst\|COUT'" { } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "0.650 ns" { CNT4B:inst|CQI[3] CNT4B:inst|COUT } "NODE_NAME" } } { "CNT4B.vhd" "" { Text "E:/EDA/实验六/CNT4B.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.374 ns) + CELL(0.935 ns) 8.965 ns CNT4B:inst5\|CQI\[0\] 4 REG LC_X26_Y6_N6 7 " "Info: 4: + IC(4.374 ns) + CELL(0.935 ns) = 8.965 ns; Loc. = LC_X26_Y6_N6; Fanout = 7; REG Node = 'CNT4B:inst5\|CQI\[0\]'" { } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "5.309 ns" { CNT4B:inst|COUT CNT4B:inst5|CQI[0] } "NODE_NAME" } } { "CNT4B.vhd" "" { Text "E:/EDA/实验六/CNT4B.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.582 ns) + CELL(0.114 ns) 9.661 ns CNT4B:inst5\|COUT 5 COMB LC_X26_Y6_N5 4 " "Info: 5: + IC(0.582 ns) + CELL(0.114 ns) = 9.661 ns; Loc. = LC_X26_Y6_N5; Fanout = 4; COMB Node = 'CNT4B:inst5\|COUT'" { } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "0.696 ns" { CNT4B:inst5|CQI[0] CNT4B:inst5|COUT } "NODE_NAME" } } { "CNT4B.vhd" "" { Text "E:/EDA/实验六/CNT4B.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.650 ns) + CELL(0.935 ns) 14.246 ns CNT4B:inst6\|CQI\[0\] 6 REG LC_X23_Y7_N0 7 " "Info: 6: + IC(3.650 ns) + CELL(0.935 ns) = 14.246 ns; Loc. = LC_X23_Y7_N0; Fanout = 7; REG Node = 'CNT4B:inst6\|CQI\[0\]'" { } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "4.585 ns" { CNT4B:inst5|COUT CNT4B:inst6|CQI[0] } "NODE_NAME" } } { "CNT4B.vhd" "" { Text "E:/EDA/实验六/CNT4B.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.612 ns) + CELL(0.114 ns) 14.972 ns CNT4B:inst6\|COUT 7 COMB LC_X23_Y7_N6 4 " "Info: 7: + IC(0.612 ns) + CELL(0.114 ns) = 14.972 ns; Loc. = LC_X23_Y7_N6; Fanout = 4; COMB Node = 'CNT4B:inst6\|COUT'" { } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "0.726 ns" { CNT4B:inst6|CQI[0] CNT4B:inst6|COUT } "NODE_NAME" } } { "CNT4B.vhd" "" { Text "E:/EDA/实验六/CNT4B.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.421 ns) + CELL(0.711 ns) 20.104 ns CNT4B:inst7\|CQI\[3\] 8 REG LC_X23_Y8_N2 3 " "Info: 8: + IC(4.421 ns) + CELL(0.711 ns) = 20.104 ns; Loc. = LC_X23_Y8_N2; Fanout = 3; REG Node = 'CNT4B:inst7\|CQI\[3\]'" { } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "5.132 ns" { CNT4B:inst6|COUT CNT4B:inst7|CQI[3] } "NODE_NAME" } } { "CNT4B.vhd" "" { Text "E:/EDA/实验六/CNT4B.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.327 ns ( 26.50 % ) " "Info: Total cell delay = 5.327 ns ( 26.50 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "14.777 ns ( 73.50 % ) " "Info: Total interconnect delay = 14.777 ns ( 73.50 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "20.104 ns" { CLK CNT4B:inst|CQI[3] CNT4B:inst|COUT CNT4B:inst5|CQI[0] CNT4B:inst5|COUT CNT4B:inst6|CQI[0] CNT4B:inst6|COUT CNT4B:inst7|CQI[3] } "NODE_NAME" } } { "e:/eda/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/eda/quartus/bin/Technology_Viewer.qrui" "20.104 ns" { CLK CLK~out0 CNT4B:inst|CQI[3] CNT4B:inst|COUT CNT4B:inst5|CQI[0] CNT4B:inst5|COUT CNT4B:inst6|CQI[0] CNT4B:inst6|COUT CNT4B:inst7|CQI[3] } { 0.000ns 0.000ns 0.602ns 0.536ns 4.374ns 0.582ns 3.650ns 0.612ns 4.421ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.935ns 0.114ns 0.935ns 0.114ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 20.644 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 20.644 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 4; CLK Node = 'CLK'" { } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "deccounter.bdf" "" { Schematic "E:/EDA/实验六/deccounter.bdf" { { 24 -88 80 40 "CLK" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.935 ns) 3.006 ns CNT4B:inst\|CQI\[0\] 2 REG LC_X26_Y7_N9 7 " "Info: 2: + IC(0.602 ns) + CELL(0.935 ns) = 3.006 ns; Loc. = LC_X26_Y7_N9; Fanout = 7; REG Node = 'CNT4B:inst\|CQI\[0\]'" { } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "1.537 ns" { CLK CNT4B:inst|CQI[0] } "NODE_NAME" } } { "CNT4B.vhd" "" { Text "E:/EDA/实验六/CNT4B.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.597 ns) + CELL(0.292 ns) 3.895 ns CNT4B:inst\|COUT 3 COMB LC_X26_Y7_N4 4 " "Info: 3: + IC(0.597 ns) + CELL(0.292 ns) = 3.895 ns; Loc. = LC_X26_Y7_N4; Fanout = 4; COMB Node = 'CNT4B:inst\|COUT'" { } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "0.889 ns" { CNT4B:inst|CQI[0] CNT4B:inst|COUT } "NODE_NAME" } } { "CNT4B.vhd" "" { Text "E:/EDA/实验六/CNT4B.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.374 ns) + CELL(0.935 ns) 9.204 ns CNT4B:inst5\|CQI\[3\] 4 REG LC_X26_Y6_N2 4 " "Info: 4: + IC(4.374 ns) + CELL(0.935 ns) = 9.204 ns; Loc. = LC_X26_Y6_N2; Fanout = 4; REG Node = 'CNT4B:inst5\|CQI\[3\]'" { } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "5.309 ns" { CNT4B:inst|COUT CNT4B:inst5|CQI[3] } "NODE_NAME" } } { "CNT4B.vhd" "" { Text "E:/EDA/实验六/CNT4B.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.567 ns) + CELL(0.292 ns) 10.063 ns CNT4B:inst5\|COUT 5 COMB LC_X26_Y6_N5 4 " "Info: 5: + IC(0.567 ns) + CELL(0.292 ns) = 10.063 ns; Loc. = LC_X26_Y6_N5; Fanout = 4; COMB Node = 'CNT4B:inst5\|COUT'" { } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "0.859 ns" { CNT4B:inst5|CQI[3] CNT4B:inst5|COUT } "NODE_NAME" } } { "CNT4B.vhd" "" { Text "E:/EDA/实验六/CNT4B.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.650 ns) + CELL(0.935 ns) 14.648 ns CNT4B:inst6\|CQI\[3\] 6 REG LC_X23_Y7_N2 4 " "Info: 6: + IC(3.650 ns) + CELL(0.935 ns) = 14.648 ns; Loc. = LC_X23_Y7_N2; Fanout = 4; REG Node = 'CNT4B:inst6\|CQI\[3\]'" { } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "4.585 ns" { CNT4B:inst5|COUT CNT4B:inst6|CQI[3] } "NODE_NAME" } } { "CNT4B.vhd" "" { Text "E:/EDA/实验六/CNT4B.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.572 ns) + CELL(0.292 ns) 15.512 ns CNT4B:inst6\|COUT 7 COMB LC_X23_Y7_N6 4 " "Info: 7: + IC(0.572 ns) + CELL(0.292 ns) = 15.512 ns; Loc. = LC_X23_Y7_N6; Fanout = 4; COMB Node = 'CNT4B:inst6\|COUT'" { } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "0.864 ns" { CNT4B:inst6|CQI[3] CNT4B:inst6|COUT } "NODE_NAME" } } { "CNT4B.vhd" "" { Text "E:/EDA/实验六/CNT4B.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.421 ns) + CELL(0.711 ns) 20.644 ns CNT4B:inst7\|CQI\[3\] 8 REG LC_X23_Y8_N2 3 " "Info: 8: + IC(4.421 ns) + CELL(0.711 ns) = 20.644 ns; Loc. = LC_X23_Y8_N2; Fanout = 3; REG Node = 'CNT4B:inst7\|CQI\[3\]'" { } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "5.132 ns" { CNT4B:inst6|COUT CNT4B:inst7|CQI[3] } "NODE_NAME" } } { "CNT4B.vhd" "" { Text "E:/EDA/实验六/CNT4B.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.861 ns ( 28.39 % ) " "Info: Total cell delay = 5.861 ns ( 28.39 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "14.783 ns ( 71.61 % ) " "Info: Total interconnect delay = 14.783 ns ( 71.61 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "20.644 ns" { CLK CNT4B:inst|CQI[0] CNT4B:inst|COUT CNT4B:inst5|CQI[3] CNT4B:inst5|COUT CNT4B:inst6|CQI[3] CNT4B:inst6|COUT CNT4B:inst7|CQI[3] } "NODE_NAME" } } { "e:/eda/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/eda/quartus/bin/Technology_Viewer.qrui" "20.644 ns" { CLK CLK~out0 CNT4B:inst|CQI[0] CNT4B:inst|COUT CNT4B:inst5|CQI[3] CNT4B:inst5|COUT CNT4B:inst6|CQI[3] CNT4B:inst6|COUT CNT4B:inst7|CQI[3] } { 0.000ns 0.000ns 0.602ns 0.597ns 4.374ns 0.567ns 3.650ns 0.572ns 4.421ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.935ns 0.292ns 0.935ns 0.292ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "20.104 ns" { CLK CNT4B:inst|CQI[3] CNT4B:inst|COUT CNT4B:inst5|CQI[0] CNT4B:inst5|COUT CNT4B:inst6|CQI[0] CNT4B:inst6|COUT CNT4B:inst7|CQI[3] } "NODE_NAME" } } { "e:/eda/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/eda/quartus/bin/Technology_Viewer.qrui" "20.104 ns" { CLK CLK~out0 CNT4B:inst|CQI[3] CNT4B:inst|COUT CNT4B:inst5|CQI[0] CNT4B:inst5|COUT CNT4B:inst6|CQI[0] CNT4B:inst6|COUT CNT4B:inst7|CQI[3] } { 0.000ns 0.000ns 0.602ns 0.536ns 4.374ns 0.582ns 3.650ns 0.612ns 4.421ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.935ns 0.114ns 0.935ns 0.114ns 0.711ns } "" } } { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "20.644 ns" { CLK CNT4B:inst|CQI[0] CNT4B:inst|COUT CNT4B:inst5|CQI[3] CNT4B:inst5|COUT CNT4B:inst6|CQI[3] CNT4B:inst6|COUT CNT4B:inst7|CQI[3] } "NODE_NAME" } } { "e:/eda/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/eda/quartus/bin/Technology_Viewer.qrui" "20.644 ns" { CLK CLK~out0 CNT4B:inst|CQI[0] CNT4B:inst|COUT CNT4B:inst5|CQI[3] CNT4B:inst5|COUT CNT4B:inst6|CQI[3] CNT4B:inst6|COUT CNT4B:inst7|CQI[3] } { 0.000ns 0.000ns 0.602ns 0.597ns 4.374ns 0.567ns 3.650ns 0.572ns 4.421ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.935ns 0.292ns 0.935ns 0.292ns 0.711ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "CNT4B.vhd" "" { Text "E:/EDA/实验六/CNT4B.vhd" 16 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "CNT4B.vhd" "" { Text "E:/EDA/实验六/CNT4B.vhd" 16 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "1.260 ns" { CNT4B:inst7|CQI[3] CNT4B:inst7|CQI[3] } "NODE_NAME" } } { "e:/eda/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/eda/quartus/bin/Technology_Viewer.qrui" "1.260 ns" { CNT4B:inst7|CQI[3] CNT4B:inst7|CQI[3] } { 0.000ns 0.522ns } { 0.000ns 0.738ns } "" } } { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "20.104 ns" { CLK CNT4B:inst|CQI[3] CNT4B:inst|COUT CNT4B:inst5|CQI[0] CNT4B:inst5|COUT CNT4B:inst6|CQI[0] CNT4B:inst6|COUT CNT4B:inst7|CQI[3] } "NODE_NAME" } } { "e:/eda/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/eda/quartus/bin/Technology_Viewer.qrui" "20.104 ns" { CLK CLK~out0 CNT4B:inst|CQI[3] CNT4B:inst|COUT CNT4B:inst5|CQI[0] CNT4B:inst5|COUT CNT4B:inst6|CQI[0] CNT4B:inst6|COUT CNT4B:inst7|CQI[3] } { 0.000ns 0.000ns 0.602ns 0.536ns 4.374ns 0.582ns 3.650ns 0.612ns 4.421ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.935ns 0.114ns 0.935ns 0.114ns 0.711ns } "" } } { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "20.644 ns" { CLK CNT4B:inst|CQI[0] CNT4B:inst|COUT CNT4B:inst5|CQI[3] CNT4B:inst5|COUT CNT4B:inst6|CQI[3] CNT4B:inst6|COUT CNT4B:inst7|CQI[3] } "NODE_NAME" } } { "e:/eda/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/eda/quartus/bin/Technology_Viewer.qrui" "20.644 ns" { CLK CLK~out0 CNT4B:inst|CQI[0] CNT4B:inst|COUT CNT4B:inst5|CQI[3] CNT4B:inst5|COUT CNT4B:inst6|CQI[3] CNT4B:inst6|COUT CNT4B:inst7|CQI[3] } { 0.000ns 0.000ns 0.602ns 0.597ns 4.374ns 0.567ns 3.650ns 0.572ns 4.421ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.935ns 0.292ns 0.935ns 0.292ns 0.711ns } "" } } } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0} } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "" { CNT4B:inst7|CQI[3] } "NODE_NAME" } } { "e:/eda/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/eda/quartus/bin/Technology_Viewer.qrui" "" { CNT4B:inst7|CQI[3] } { } { } "" } } { "CNT4B.vhd" "" { Text "E:/EDA/实验六/CNT4B.vhd" 16 -1 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLKK OUT1\[3\] REG4B:inst2\|DOUT\[3\] 14.219 ns register " "Info: tco from clock \"CLKK\" to destination pin \"OUT1\[3\]\" through register \"REG4B:inst2\|DOUT\[3\]\" is 14.219 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLKK source 8.350 ns + Longest register " "Info: + Longest clock path from clock \"CLKK\" to source register is 8.350 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns CLKK 1 CLK PIN_47 5 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_47; Fanout = 5; CLK Node = 'CLKK'" { } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLKK } "NODE_NAME" } } { "deccounter.bdf" "" { Schematic "E:/EDA/实验六/deccounter.bdf" { { 120 -88 80 136 "CLKK" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.717 ns) + CELL(0.935 ns) 4.127 ns TESTCTL:inst8\|DIV2CLK 2 REG LC_X8_Y6_N0 37 " "Info: 2: + IC(1.717 ns) + CELL(0.935 ns) = 4.127 ns; Loc. = LC_X8_Y6_N0; Fanout = 37; REG Node = 'TESTCTL:inst8\|DIV2CLK'" { } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "2.652 ns" { CLKK TESTCTL:inst8|DIV2CLK } "NODE_NAME" } } { "TESTCTL.vhd" "" { Text "E:/EDA/实验六/TESTCTL.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.512 ns) + CELL(0.711 ns) 8.350 ns REG4B:inst2\|DOUT\[3\] 3 REG LC_X26_Y9_N2 1 " "Info: 3: + IC(3.512 ns) + CELL(0.711 ns) = 8.350 ns; Loc. = LC_X26_Y9_N2; Fanout = 1; REG Node = 'REG4B:inst2\|DOUT\[3\]'" { } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "4.223 ns" { TESTCTL:inst8|DIV2CLK REG4B:inst2|DOUT[3] } "NODE_NAME" } } { "REG4B.vhd" "" { Text "E:/EDA/实验六/REG4B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.121 ns ( 37.38 % ) " "Info: Total cell delay = 3.121 ns ( 37.38 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.229 ns ( 62.62 % ) " "Info: Total interconnect delay = 5.229 ns ( 62.62 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "8.350 ns" { CLKK TESTCTL:inst8|DIV2CLK REG4B:inst2|DOUT[3] } "NODE_NAME" } } { "e:/eda/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/eda/quartus/bin/Technology_Viewer.qrui" "8.350 ns" { CLKK CLKK~out0 TESTCTL:inst8|DIV2CLK REG4B:inst2|DOUT[3] } { 0.000ns 0.000ns 1.717ns 3.512ns } { 0.000ns 1.475ns 0.935ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "REG4B.vhd" "" { Text "E:/EDA/实验六/REG4B.vhd" 12 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.645 ns + Longest register pin " "Info: + Longest register to pin delay is 5.645 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns REG4B:inst2\|DOUT\[3\] 1 REG LC_X26_Y9_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y9_N2; Fanout = 1; REG Node = 'REG4B:inst2\|DOUT\[3\]'" { } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "" { REG4B:inst2|DOUT[3] } "NODE_NAME" } } { "REG4B.vhd" "" { Text "E:/EDA/实验六/REG4B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.521 ns) + CELL(2.124 ns) 5.645 ns OUT1\[3\] 2 PIN PIN_11 0 " "Info: 2: + IC(3.521 ns) + CELL(2.124 ns) = 5.645 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'OUT1\[3\]'" { } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "5.645 ns" { REG4B:inst2|DOUT[3] OUT1[3] } "NODE_NAME" } } { "deccounter.bdf" "" { Schematic "E:/EDA/实验六/deccounter.bdf" { { 200 736 912 216 "OUT1\[3..0\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 37.63 % ) " "Info: Total cell delay = 2.124 ns ( 37.63 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.521 ns ( 62.37 % ) " "Info: Total interconnect delay = 3.521 ns ( 62.37 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "5.645 ns" { REG4B:inst2|DOUT[3] OUT1[3] } "NODE_NAME" } } { "e:/eda/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/eda/quartus/bin/Technology_Viewer.qrui" "5.645 ns" { REG4B:inst2|DOUT[3] OUT1[3] } { 0.000ns 3.521ns } { 0.000ns 2.124ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "8.350 ns" { CLKK TESTCTL:inst8|DIV2CLK REG4B:inst2|DOUT[3] } "NODE_NAME" } } { "e:/eda/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/eda/quartus/bin/Technology_Viewer.qrui" "8.350 ns" { CLKK CLKK~out0 TESTCTL:inst8|DIV2CLK REG4B:inst2|DOUT[3] } { 0.000ns 0.000ns 1.717ns 3.512ns } { 0.000ns 1.475ns 0.935ns 0.711ns } "" } } { "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/quartus/bin/TimingClosureFloorplan.fld" "" "5.645 ns" { REG4B:inst2|DOUT[3] OUT1[3] } "NODE_NAME" } } { "e:/eda/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/eda/quartus/bin/Technology_Viewer.qrui" "5.645 ns" { REG4B:inst2|DOUT[3] OUT1[3] } { 0.000ns 3.521ns } { 0.000ns 2.124ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
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