📄 deccounter.sim.rpt
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; Overwrite Waveform Inputs With Simulation Outputs ; Off ; ;
; Perform Glitch Filtering in Timing Simulation ; Auto ; Auto ;
+--------------------------------------------------------------------------------------------+----------------+---------------+
+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.
+--------------------------------------------------------------------+
; Coverage Summary ;
+-----------------------------------------------------+--------------+
; Type ; Value ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage ; 16.30 % ;
; Total nodes checked ; 215 ;
; Total output ports checked ; 227 ;
; Total output ports with complete 1/0-value coverage ; 37 ;
; Total output ports with no 1/0-value coverage ; 188 ;
; Total output ports with no 1-value coverage ; 188 ;
; Total output ports with no 0-value coverage ; 190 ;
+-----------------------------------------------------+--------------+
The following table displays output ports that toggle between 1 and 0 during simulation.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage ;
+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------------+
; |deccounter|CLKK ; |deccounter|CLKK ; out ;
; |deccounter|CLK ; |deccounter|CLK ; out ;
; |deccounter|CNT4B:inst7|CQI[3]~0 ; |deccounter|CNT4B:inst7|CQI[3]~0 ; out0 ;
; |deccounter|CNT4B:inst6|CQI[3]~0 ; |deccounter|CNT4B:inst6|CQI[3]~0 ; out0 ;
; |deccounter|CNT4B:inst5|CQI[3]~0 ; |deccounter|CNT4B:inst5|CQI[3]~0 ; out0 ;
; |deccounter|CNT4B:inst|CQI[0] ; |deccounter|CNT4B:inst|CQI[0] ; regout ;
; |deccounter|CNT4B:inst|CQI[2] ; |deccounter|CNT4B:inst|CQI[2] ; regout ;
; |deccounter|CNT4B:inst|CQI[1] ; |deccounter|CNT4B:inst|CQI[1] ; regout ;
; |deccounter|CNT4B:inst|CQI[3]~0 ; |deccounter|CNT4B:inst|CQI[3]~0 ; out0 ;
; |deccounter|TESTCTL:inst8|RST_CNT ; |deccounter|TESTCTL:inst8|RST_CNT ; out0 ;
; |deccounter|TESTCTL:inst8|DIV2CLK ; |deccounter|TESTCTL:inst8|DIV2CLK ; regout ;
; |deccounter|CNT4B:inst|lpm_add_sub:Add0|result_node[0] ; |deccounter|CNT4B:inst|lpm_add_sub:Add0|result_node[0] ; out0 ;
; |deccounter|CNT4B:inst|lpm_add_sub:Add0|result_node[1] ; |deccounter|CNT4B:inst|lpm_add_sub:Add0|result_node[1] ; out0 ;
; |deccounter|CNT4B:inst|lpm_add_sub:Add0|result_node[2] ; |deccounter|CNT4B:inst|lpm_add_sub:Add0|result_node[2] ; out0 ;
; |deccounter|CNT4B:inst|lpm_add_sub:Add0|result_node[3] ; |deccounter|CNT4B:inst|lpm_add_sub:Add0|result_node[3] ; out0 ;
; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]~0 ; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]~0 ; out0 ;
; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0] ; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0] ; out0 ;
; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|_~0 ; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|_~0 ; out0 ;
; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|_~3 ; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|_~3 ; out0 ;
; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]~2 ; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]~2 ; out0 ;
; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]~3 ; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]~3 ; out0 ;
; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3] ; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3] ; out0 ;
; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2] ; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2] ; out0 ;
; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1] ; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1] ; out0 ;
; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|_~8 ; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|_~8 ; out0 ;
; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|_~9 ; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|_~9 ; out0 ;
; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|_~11 ; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|_~11 ; out0 ;
; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|_~12 ; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|_~12 ; out0 ;
; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|_~14 ; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|_~14 ; out0 ;
; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|_~15 ; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|_~15 ; out0 ;
; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; sout ;
; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] ; cout ;
; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; sout ;
; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] ; cout ;
; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; sout ;
; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] ; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] ; cout ;
; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] ; |deccounter|CNT4B:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] ; sout ;
+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 1 during simulation.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage ;
+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------+
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